公开(公告)号：US07895469B2

公开(公告)日：2011-02-22

申请号：US12285796

申请日：2008-10-14

申请人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

发明人： Emre Özer ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/00

CPC分类号： G06F9/3842 ,  G06F9/3861 ,  G06F9/3869

摘要： An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first error recovery operation (partial pipeline flushing) if such speculative processing is determined to be based upon an error. The pipeline stage 10 further includes speculative error detecting circuitry 14 which generates a prediction nc regarding whether or not the processing circuitry 18 will produce an error. This prediction is used to trigger a second error recovery operation (partial pipeline stall). This second error recovery operation has a lower performance penalty than the first error recovery operation.

摘要翻译： 集成电路2设置有多个流水线级10.这些流水线级10具有推测性处理控制电路12，其允许下游流水线级的推测性处理，并且如果确定了这种推测性处理，则触发第一错误恢复操作（部分流水线冲洗） 基于错误。 流水线级10还包括推测性错误检测电路14，其产生关于处理电路18是否将产生错误的预测nc。 该预测用于触发第二次错误恢复操作（部分流水线停止）。 该第二错误恢复操作具有比第一错误恢复操作更低的性能损失。

公开(公告)号：US20100064287A1

公开(公告)日：2010-03-11

申请号：US12458699

申请日：2009-07-21

申请人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

发明人： David Michael Bull ,  Emre Ozer ,  Shidhartha Das

IPC分类号： G06F9/30 ,  G06F11/07 ,  G06F9/46

CPC分类号： G06F9/3836 ,  G06F9/3861 ,  G06F9/3869 ,  G06F9/3891 ,  G06F11/004 ,  G06F11/1405

摘要： A processor 2 is responsive to a stream of program instructions to issue program instructions under control of scheduling circuitry 6 to respective execution units 24 for execution. The execution units 24 can include error detecting circuitry 32 for detecting a change in an output signal which occurs after the output signal has latched and during an error detecting period following the latching of the output signal. The scheduling circuitry 6 is arranged so as to suppress issue of program instructions to an execution unit 24 having such error detecting circuitry 32 on consecutive processing cycles.

摘要翻译： 处理器2响应于程序指令流，以在调度电路6的控制下发出程序指令，以执行相应的执行单元24。 执行单元24可以包括用于检测在输出信号被锁存之后和在锁存输出信号之后的错误检测周期期间发生的输出信号的变化的错误检测电路32。 调度电路6被布置为在连续的处理周期中抑制对具有这种错误检测电路32的执行单元24的程序指令的发出。

公开(公告)号：US20090282281A1

公开(公告)日：2009-11-12

申请号：US12285373

申请日：2008-10-02

申请人： David Michael Bull ,  Ganesh Suryanarayan Dasika

发明人： David Michael Bull ,  Ganesh Suryanarayan Dasika

IPC分类号： G06F11/07

CPC分类号： G06F11/004 ,  G06F9/3869 ,  G06F11/0793

摘要： To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one functional element. At least one functional element includes error detection/recovery circuitry. The flow of input values to the first evaluation stage in the compound functional unit is controlled so that the input values are changed at most every second clock cycle.

摘要翻译： 为了防止在具有错误检测和恢复机制的系统中发生短路径错误，将功能元件组合以形成包括至少两个评估阶段的复合功能单元，每个评估阶段包括至少一个功能元件。 至少一个功能元件包括错误检测/恢复电路。 对复合功能单元中的第一评估阶段的输入值的流程进行控制，使得输入值最多每隔一个时钟周期改变。

公开(公告)号：US08555124B2

公开(公告)日：2013-10-08

申请号：US12801402

申请日：2010-06-07

申请人： Sachin Satish Idgunji ,  Shidhartha Das ,  David Michael Bull ,  Robert Campbell Aitken

发明人： Sachin Satish Idgunji ,  Shidhartha Das ,  David Michael Bull ,  Robert Campbell Aitken

IPC分类号： G01R31/28

CPC分类号： G01R31/3016

摘要： An apparatus and method are provided for detecting an approaching error condition within a data processing apparatus and includes a sequential storage structure arranged to latch an output signal generated by combinatorial circuitry dependent on a second clock signal. The sequential storage structure has a main storage element to latch a value of the output signal for provision to subsequent combinatorial circuitry. The sequential storage structure can be operated in either first or second modes of operation where, in the first mode, the predetermined timing window is ahead of a time at which the main storage element latches said value of the output signal enabling an approaching setup timing error to be detected. In the second mode, the predetermined timing window is after the time at which the main storage element latches said value of the output signal where an approaching hold timing error is detected.

摘要翻译： 提供了一种用于检测数据处理装置内接近的错误状况的装置和方法，并且包括顺序存储结构，其被布置为根据第二时钟信号锁存由组合电路产生的输出信号。 顺序存储结构具有主存储元件以锁存输出信号的值以供给后续的组合电路。 顺序存储结构可以在第一或第二操作模式中操作，其中在第一模式中，预定定时窗口在主存储元件锁存输出信号的所述值以使得能够接近建立定时误差的时间之前 被检测。 在第二模式中，预定定时窗口在主存储元件锁存检测到接近保持定时误差的输出信号的值之后。

公开(公告)号：US20130169350A1

公开(公告)日：2013-07-04

申请号：US13341547

申请日：2011-12-30

申请人： Paul Nicholas WHATMOUGH ,  David Michael Bull ,  Shidhartha Das

发明人： Paul Nicholas WHATMOUGH ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G11C5/14

CPC分类号： G01R31/3004 ,  G01R31/30

摘要： An integrated circuit comprising a plurality of sensors configured to sense variations in supply voltage levels at points within the integrated circuit is disclosed. The plurality of sensors are distributed across the integrated circuit and have transistor devices such that process variations in the transistor devices within the sensors are such that a sensing result will have a random voltage offset that has a predetermined probability of lying within a pre-defined voltage offset range. The integrated circuit is configured to transmit results from multiple ones of the plurality of sensors to processing circuitry such that the variations in the supply voltage levels can be determined with a voltage offset range that is reduced compared to the pre-defined voltage offset range.

摘要翻译： 公开了一种集成电路，其包括被配置为感测集成电路内的点处的电源电压电平的变化的多个传感器。 多个传感器分布在整个集成电路上并且具有晶体管器件，使得传感器内的晶体管器件中的工艺变化使得感测结果将具有位于预定电压内的预定概率的随机电压偏移 偏移范围。 集成电路被配置为将结果从多个传感器中的多个传感器传送到处理电路，使得可以利用与预定电压偏移范围相比减小的电压偏移范围来确定电源电压电平的变化。

公开(公告)号：US20120216067A1

公开(公告)日：2012-08-23

申请号：US12929848

申请日：2011-02-18

申请人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das

发明人： Paul Nicholas Whatmough ,  David Michael Bull ,  Shidhartha Das

IPC分类号： G06F11/07

CPC分类号： G06F1/324 ,  G06F1/3296 ,  G06F11/076 ,  Y02D10/126 ,  Y02D10/172

摘要： A data processing apparatus and method are provided that use monitoring circuitry to control operating parameters of the data processing apparatus. The data processing apparatus has functional circuitry for performing data processing, the functional circuitry including error correction circuitry configured to detect errors in operation of the functional circuitry and to repair those errors in operation. Tuneable monitoring circuitry monitors a characteristic indicative of changes in signal propagation delay within the functional circuitry and produces a control signal dependent on the monitored characteristic. In a continuous tuning mode operation, the tuneable monitoring circuitry modifies the dependency between the monitored characteristic and the control signal in dependence upon certain characteristics of the errors detected by the error correction circuitry. An operating parameter controller is then arranged, in the continuous mode of operation, to control one or more performance controlling operating parameters of the data processing apparatus in dependence upon the control signal. This enables efficient and robust control of those operating parameters in response to changes in environmental conditions.

摘要翻译： 提供一种使用监视电路来控制数据处理装置的操作参数的数据处理装置和方法。 所述数据处理装置具有用于执行数据处理的功能电路，所述功能电路包括错误校正电路，其被配置为检测功能电路的操作中的错误并修复这些操作中的错误。 可调节监控电路监视指示功能电路内的信号传播延迟的变化的特性，并产生取决于被监测特性的控制信号。 在连续调谐模式操作中，可调谐监视电路根据由纠错电路检测到的错误的某些特性来修改监视特性和控制信号之间的相关性。 然后，在连续操作模式下，设置操作参数控制器，以根据控制信号控制数据处理装置的一个或多个性能控制操作参数。 这可以响应于环境条件的变化而对这些操作参数进行有效和鲁棒的控制。

公开(公告)号：US08185791B2

公开(公告)日：2012-05-22

申请号：US12453835

申请日：2009-05-22

申请人： David Michael Bull ,  Shidhartha Das

发明人： David Michael Bull ,  Shidhartha Das

IPC分类号： G01R31/28

CPC分类号： G06F1/10 ,  G06F11/0757 ,  G06F11/0793

摘要： Tuning limits are set for operational parameters in a processing stage within a data processing apparatus for processing a signal and outputting it at an output time. If a signal output between the output time and a predetermined time later does not have a stable value, the predetermined time later being before a next output time, an error is signaled. A tuning circuit adjusts an operational parameter of the processing stage in accordance with a tuning limit. A signal passing along a critical path of the processing stage tuned to the tuning limit is expected to reach the output of the processing stage at a preset time later than the output time, the preset time being less than the predetermined time.

摘要翻译： 在处理信号并在输出时输出信号的数据处理装置内的处理级的操作参数设定调谐限制。 如果在输出时间和预定时间之后的信号输出不具有稳定值，则之后的预定时间在下一个输出时间之前，发出错误信号。 调谐电路根据调谐限制调整处理级的操作参数。 调整到调谐极限的处理级的关键路径的信号预计在比输出时间晚的预设时间到达处理级的输出，预设时间小于预定时间。

公开(公告)号：US07979642B2

公开(公告)日：2011-07-12

申请号：US12232188

申请日：2008-09-11

申请人： David Michael Bull ,  Emre Özer

发明人： David Michael Bull ,  Emre Özer

IPC分类号： G06F13/00

CPC分类号： G06F12/126 ,  G06F9/3806 ,  G06F9/3851

摘要： A data processing apparatus is provided comprising processing circuitry for executing multiple program threads. At least one storage unit is shared between the multiple program threads and comprises multiple entries, each entry for storing a storage item either associated with a high priority program thread or a lower priority program thread. A history storage for retaining a history field for each of a plurality of blocks of the storage unit is also provided. On detection of a high priority storage item being evicted from the storage unit as a result of allocation to that entry of a lower priority storage item, the history field for the block containing that entry is populated with an indication of the evicted high priority storage item. When later a high priority storage item is allocated to a selected entry of the storage unit, a comparison operation between the allocated high priority storage item and the indication in the history field for the block containing the selected entry is carried out, and on detection of a match condition a lock indication associated with that entry is set to inhibit further eviction of that high priority storage item.

摘要翻译： 提供了一种数据处理装置，包括用于执行多个程序线程的处理电路。 至少一个存储单元在多个程序线程之间共享并且包括多个条目，每个条目用于存储与高优先级程序线程或较低优先级程序线程相关联的存储项目。 还提供了用于保存存储单元的多个块中的每一个的历史字段的历史存储器。 在检测到作为对较低优先级存储项目的该条目的分配的结果被从存储单元驱逐的高优先级存储项目时，包含该条目的块的历史字段填充有被驱逐的高优先级存储项目的指示 。 当稍后将高优先级存储项目分配给存储单元的所选条目时，执行所分配的高优先级存储项目与包含所选择的条目的块的历史字段中的指示之间的比较操作，并且在检测到 匹配条件与该条目相关联的锁定指示被设置为禁止进一步驱逐该高优先级存储项目。

公开(公告)号：US20100275080A1

公开(公告)日：2010-10-28

申请号：US12735339

申请日：2008-12-29

申请人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

发明人： Shidhartha Das ,  David Michael Bull ,  Emre Ozer

IPC分类号： G06F11/07

CPC分类号： G06F11/0793 ,  G01R31/31816 ,  G06F11/1076 ,  G06F11/1608

摘要： An integrated circuit (2) is provided with error detection circuitry (10,12) and error repair circuitry (14). Error tolerance circuitry (16) is responsive to a control parameter to selectively disable the error repair circuitry (14). The control parameter is dependent on the processing performed within the circuit. For example, the control parameter may be generated in dependence upon the program instruction being executed, the output signal value which is in error, the previous behaviour of the circuit or in other ways.

摘要翻译： 集成电路（2）具有错误检测电路（10,12）和错误修复电路（14）。 误差容限电路（16）响应于控制参数来选择性地禁用误差修复电路（14）。 控制参数取决于电路内执行的处理。 例如，控制参数可以根据执行的程序指令，错误的输出信号值，电路的先前行为或其他方式来生成。

公开(公告)号：US20100134148A1

公开(公告)日：2010-06-03

申请号：US12591436

申请日：2009-11-19

申请人： David Michael Bull

发明人： David Michael Bull

IPC分类号： H03K19/00

CPC分类号： G11C8/18 ,  G11C27/02 ,  H03K5/1534 ,  H03K5/19

摘要： Transition detection circuitry for detecting during multiple clock cycles, transitions occurring within a detection period in each of said multiple clock cycles at a plurality of nodes within a circuit is disclosed. The transition detection circuitry comprises: a clock signal generator for generating a detection clock signal from a clock signal clocking a sampling element within said circuit, said detection clock signal defining said detection period; a plurality of transition detectors for detecting transitions at respective ones of said plurality of nodes during said detection period, each of said plurality of transition detectors being clocked by said detection clock signal; and combining circuitry for combining said detected transitions output by said plurality of transition detectors to generate a composite transition detection signal.

摘要翻译： 公开了用于在多个时钟周期期间检测的转换检测电路，在电路内的多个节点处在所述多个时钟周期的每一个中的检测周期内发生的转换。 转移检测电路包括：时钟信号发生器，用于从对所述电路内的采样元件计时的时钟信号产生检测时钟信号，所述检测时钟信号定义所述检测周期; 多个转换检测器，用于在所述检测周期期间检测所述多个节点中各个节点的转变，所述多个转换检测器中的每一个由所述检测时钟信号计时; 以及组合电路，用于组合由所述多个转换检测器输出的所述检测到的转换，以产生复合转换检测信号。