公开(公告)号：US06570246B1

公开(公告)日：2003-05-27

申请号：US10064110

申请日：2002-06-12

Applicant: Tzung-Han Lee ,  Kun-Chi Lin

Inventor： Tzung-Han Lee ,  Kun-Chi Lin

IPC: H01L2348

CPC classification number: H01L25/0652 ,  H01L25/0655 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/01015 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/01033

Abstract: A multi-chip package which has a L-shaped plate and a plurality of dies arranged on the L-shaped plate. The L-shaped plate has a die package region, a plurality of solder bump pads disposed in the die package region, a plurality of pins electrically connected to a printed circuit board (PCB), and an internal circuit inside the L-shaped plate electrically connected to the plurality of solder bump pads and corresponding pins. Each die includes a plurality of bonding pads on an active surface of the die, and the bonding pads are electrically connected to corresponding solder bump pads.

Abstract translation: 一种具有L形板和布置在L形板上的多个管芯的多芯片封装。 L形板具有管芯封装区域，设置在管芯封装区域中的多个焊料凸块焊盘，电连接到印刷电路板（PCB）的多个引脚，以及L形板内部的电路内部电路 连接到多个焊料凸块和相应的引脚。 每个管芯包括在管芯的有效表面上的多个接合焊盘，并且焊盘与相应的焊料凸块焊接电连接。

公开(公告)号：US06465360B2

公开(公告)日：2002-10-15

申请号：US09532282

申请日：2000-03-23

Applicant: Jin-Sheng Yang ,  Tzung-Han Lee ,  Kun-Chi Lin

Inventor： Jin-Sheng Yang ,  Tzung-Han Lee ,  Kun-Chi Lin

IPC: H01L21302

CPC classification number: H01L21/0273 ,  H01L21/0271 ,  H01L21/31144

Abstract: A fabrication method for an ultra-small opening is described, wherein a first photoresist layer is formed on a substrate. Exposure and development processes are further conducted to transfer the desired pattern with a small opening from the mask layer onto the surface of the first photoresist layer. A plasma treatment is then conducted on the first photoresist layer, followed by coating a second photoresist layer on the first photoresist layer.

Abstract translation: 对超小型开口的制造方法进行说明，其中在基板上形成第一光致抗蚀剂层。 进一步进行曝光和显影处理以将具有小开口的所需图案从掩模层转印到第一光致抗蚀剂层的表面上。 然后在第一光致抗蚀剂层上进行等离子体处理，然后在第一光致抗蚀剂层上涂覆第二光致抗蚀剂层。

公开(公告)号：US06365955B1

公开(公告)日：2002-04-02

申请号：US09949519

申请日：2001-09-10

Applicant: Tzung-Han Lee ,  Alex Hou ,  Kun-Chi Lin

Inventor： Tzung-Han Lee ,  Alex Hou ,  Kun-Chi Lin

IPC: H01L2900

CPC classification number: H01L27/10852 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/84 ,  H01L28/91

Abstract: A cylindrical capacitor structure and a corresponding method of manufacture. To form the cylindrical capacitor, a conductive section, an etching stop layer, a first insulation layer, a bit line structure and a second insulation layer are sequentially formed over a substrate. A portion of the second insulation layer and the first insulation layer is removed until the etching stop layer is exposed. Ultimately, a plurality of gap-connected cylindrical openings and node contact openings between spacers are sequentially formed. Conductive spacers are formed on the sidewalls of the cylindrical openings and the node contact openings. In the meantime, material similar to the conductive spacers fills the small gaps, thereby forming an upper electrode for the capacitor. A dielectric layer is formed over the capacitor electrode. The exposed etching stop layer at the bottom of the contact opening is removed to expose the conductive section above the substrate. Finally, conductive material is deposited into the node contact openings and the cylindrical openings to become the lower electrodes and the node contacts respectively.

Abstract translation: 一种圆柱形电容器结构及相应的制造方法。 为了形成圆柱形电容器，在衬底上顺序地形成导电部分，蚀刻停止层，第一绝缘层，位线结构和第二绝缘层。 去除第二绝缘层和第一绝缘层的一部分直至暴露出蚀刻停止层。 最终，间隔件之间的多个间隙连接的圆柱形开口和节点接触开口顺序地形成。 导电间隔件形成在圆柱形开口和节点接触开口的侧壁上。 同时，类似于导电间隔物的材料填充小间隙，从而形成用于电容器的上电极。 在电容器电极上形成介电层。 去除接触开口底部的暴露的蚀刻停止层，以露出衬底上方的导电部分。 最后，将导电材料沉积到节点接触开口和圆柱形开口中，分别成为下部电极和节点接触。

公开(公告)号：US06218243B1

公开(公告)日：2001-04-17

申请号：US09252127

申请日：1999-02-18

Applicant: Wayne Tan ,  Kun-Chi Lin ,  Gwo-Shii Yang

Inventor： Wayne Tan ,  Kun-Chi Lin ,  Gwo-Shii Yang

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L27/10852

Abstract: A method of fabricating a DRAM capacitor includes the step of forming an insulated layer and an etching stop layer successively on a substrate having a device structure. A contact window is formed within the etching stop layer and the insulated layer. A conductive layer is formed on the etching layer to fill in the contact window and patterned to serve as a lower electrode of the capacitor. A highly doped dielectric layer is then formed on the lower electrode and a thermal process is performed to diffuse the dopants inside the highly doped dielectric layer into the surface of the lower electrode. The dielectric layer is removed. A capacitor dielectric layer and an upper electrode are successively formed on the lower electrode to complete the fabrication of the capacitor.

Abstract translation: 制造DRAM电容器的方法包括在具有器件结构的衬底上依次形成绝缘层和蚀刻停止层的步骤。 在蚀刻停止层和绝缘层内形成接触窗。 在蚀刻层上形成导电层以填充接触窗口并图案化以用作电容器的下电极。 然后在下电极上形成高掺杂的电介质层，并进行热处理，以将高掺杂电介质层内的掺杂剂扩散到下电极的表面。 去除电介质层。 电容器电介质层和上电极依次形成在下电极上以完成电容器的制造。

公开(公告)号：US6159806A

公开(公告)日：2000-12-12

申请号：US473985

申请日：1999-12-29

Applicant: Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

IPC: H01L21/8234

CPC classification number: H01L21/823468

Abstract: A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask. Subsequently, a blanket inter-plasma dielectric is deposited above the substrate. Finally, inter-polysilicon dielectric of the interior and peripheral circuit is etched anisotropically to form a plurality of contacts.

Abstract translation: 公开了一种在间隔物形成之后沉积氧化物层的方法。 由于在间隔物形成之后的氧化物层，因此大大增加了外围电路的间隔物的有效厚度。 该方法包括其中限定了内部和外围电路的衬底，其中在衬底上形成有栅极氧化层。 顺序地形成内部门和外围门。 然后，将N型离子注入到内部和外围电路的衬底中。 因此，在衬底，内部栅极和外围栅极上方沉积第二绝缘层和第三介电层，其中第二介电层被蚀刻以形成内部栅极和外围栅极的间隔物。 然后通过使用外围栅极，间隔物和沿着间隔物延伸作为掩模的第三电介质层的一部分，将N +型离子注入到衬底中以形成源极/漏极。 随后，在衬底上方沉积一层等离子体电介质。 最后，各向异性地蚀刻内部和外围电路的多晶硅间电介质以形成多个触点。

公开(公告)号：US6150263A

公开(公告)日：2000-11-21

申请号：US188920

申请日：1998-11-09

Applicant: Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

Inventor： Kevin Lin ,  Ching-Chiao Hao ,  Kun-Chi Lin

IPC: H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76885

Abstract: A method of forming small dimension wires by an isotropic removal process. The method provides a substrate with an insulation layer. A first conductive layer and a second conductive layer are formed on the insulation layer. A wire pattern is formed on a photoresist layer after the coating process and the sequential exposure and development process. Part of the second conductive layer is removed by using the wire pattern on the photoresist layer as a mask, and thus part of the second conductive layer with wires is remained. Isotropic etching the peripheral part of the second conductive layer and thus the part of wire pattern with a smaller dimension is remained. Using the wire pattern with a smaller dimension as a mask to anisotropic etch the first conductive layer until the surface of the insulation layer is exposed, and thus the process of fabricating small dimension is finished.

Abstract translation: 通过各向同性去除方法形成小尺寸线的方法。 该方法提供具有绝缘层的基板。 第一导电层和第二导电层形成在绝缘层上。 在涂布工艺和顺序曝光和显影处理之后，在光致抗蚀剂层上形成线图案。 通过使用光致抗蚀剂层上的线图案作为掩模来去除部分第二导电层，因此残留了具有导线的第二导电层的一部分。 残留了各向同性蚀刻第二导电层的周边部分，因此保留了具有较小尺寸的线图案的部分。 使用较小尺寸的导线图案作为掩模以对第一导电层进行各向异性蚀刻，直到绝缘层的表面露出，从而完成制造小尺寸的工艺。

公开(公告)号：US6100158A

公开(公告)日：2000-08-08

申请号：US302884

申请日：1999-04-30

Applicant: Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

Inventor： Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.

Abstract translation: 制造对准标记的方法。 提供具有器件区域和对准标记区域的衬底。 器件区域高于对准标记区域。 器件区域包括有源区。 在对准标记区域的边缘处的基板中形成隔离结构，同时在对准标记区域的一部分基板上形成第一电介质层。 导电层形成在衬底上。 去除导电层的一部分以在对准标记区域露出第一介电层。 将剩余的导电层图案化以在有源区域形成部件。 在衬底上形成具有光滑表面的第二电介质层以覆盖该部件。 在第二电介质层上形成导线，其中导线与对准标记区域之间的距离大于部件与对准标记区域之间的距离。

公开(公告)号：US08018211B2

公开(公告)日：2011-09-13

申请号：US12390309

申请日：2009-02-20

Applicant: Kuan-Sheng Wang ,  Kun-Chi Lin ,  Ying-Chieh Wang ,  Shu-Hao Chang

Inventor： Kuan-Sheng Wang ,  Kun-Chi Lin ,  Ying-Chieh Wang ,  Shu-Hao Chang

IPC: G05F1/10 ,  G05F5/00 ,  H02M3/00

CPC classification number: G01R19/0084

Abstract: An output voltage detecting circuit includes a conducting structure, a voltage regulator, a first resistor and a second resistor. The conducting structure includes a power output return terminal, a first contact and a second contact. A compensating voltage is generated between the first and second contacts when an output current flows through the first and second contacts. The voltage regulator adjusts a first current according to a voltage across a first circuit terminal and the ground terminal of the voltage regulator, thereby generating a detecting signal according to the first current. An output voltage across the positive power output terminal and the power output return terminal is subject to voltage division by the first and second resistors to generate a divided voltage. The voltage across the first circuit terminal and the ground terminal of the voltage regulator is equal to a difference between the divided voltage and the compensating voltage.

Abstract translation: 输出电压检测电路包括导电结构，电压调节器，第一电阻器和第二电阻器。 导电结构包括电源输出返回端子，第一触点和第二触点。 当输出电流流过第一和第二触点时，在第一和第二触点之间产生补偿电压。 电压调节器根据第一电路端子和电压调节器的接地端子之间的电压来调节第一电流，从而根据第一电流产生检测信号。 正功率输出端子和功率输出返回端子两端的输出电压经受第一和第二电阻器的分压以产生分压。 电压调节器的第一电路端子和接地端子之间的电压等于分压和补偿电压之间的差值。

公开(公告)号：US20060120120A1

公开(公告)日：2006-06-08

申请号：US10908159

申请日：2005-04-29

Applicant: Kun-Chi Lin ,  Youjun Zhang ,  Qinggang Kong ,  Junshan Lou ,  Hongjian Gan

Inventor： Kun-Chi Lin ,  Youjun Zhang ,  Qinggang Kong ,  Junshan Lou ,  Hongjian Gan

IPC: H02J1/10

CPC classification number: H02M3/285 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A power supply device and an operating method thereof are provided. The power supply device includes a main converter and an auxiliary converter. The main converter comprises a power factor corrector (PFC), a first capacitor that connects in parallel with the PFC and a DC/DC converter that connects in parallel with the first capacitor. The auxiliary converter is connected in parallel to the main converter. When the power supply device operates in a normal mode, the main converter and the auxiliary converter together provide a first output to an output load. When the power supply device is in a standby mode, the DC/DC converter is turned off so that only the auxiliary converter provides a second output to the output load. Meanwhile, the PFC is in operation to maintain the voltage of the first capacitor in order to meet the demand of the output dynamic response of the main converter.

Abstract translation: 提供电源装置及其操作方法。 电源装置包括主转换器和辅助转换器。 主转换器包括功率因数校正器（PFC），与PFC并联连接的第一电容器和与第一电容器并联连接的DC / DC转换器。 辅助转换器与主转换器并联连接。 当电源装置在正常模式下工作时，主转换器和辅助转换器一起向输出负载提供第一输出。 当电源设备处于待机模式时，DC / DC转换器关闭，只有辅助转换器向输出负载提供第二个输出。 同时，为了满足主转换器的输出动态响应的要求，PFC正在运行以维持第一电容器的电压。

公开(公告)号：US06413832B1

公开(公告)日：2002-07-02

申请号：US09755105

申请日：2001-01-08

Applicant: King-Lung Wu ,  Kun-Chi Lin

Inventor： King-Lung Wu ,  Kun-Chi Lin

IPC: H01L2120

CPC classification number: H01L27/10855 ,  H01L21/76895 ,  H01L28/60 ,  H01L28/91

Abstract: A method for forming an inner-cylindrical capacitor without top electrode mask is disclosed. The method includes a step of a trench formed on the substrate. The trench structure with a conductive layer as a first lower electrode. The first poly spacer as second lower electrode of inner-cylindrical capacitor formed on sidewall of the trench, and furthermore a dielectric layer is formed by depositing on sidewall of first poly spacer and a floor of the cylindrical trench. Then, the second poly spacer formed on sidewall of dielectric layer. The poly plug is formed by depositing polysilicon layer and polished by chemical mechanical polishing (CMP) process. Thus, an inner-cylindrical capacitor is generated.

Abstract translation: 公开了一种形成不具有顶部电极掩模的内圆柱形电容器的方法。 该方法包括形成在衬底上的沟槽的步骤。 具有导电层作为第一下电极的沟槽结构。 形成在沟槽的侧壁上的内圆柱形电容器的第二下电极的第一聚间隔物，此外，通过沉积在第一多隔离物的侧壁和圆柱形沟槽的底板上形成电介质层。 然后，形成在电介质层的侧壁上的第二聚合间隔物。 多晶硅塞通过沉积多晶硅层并通过化学机械抛光（CMP）工艺抛光而形成。 因此，产生内圆柱形电容器。