公开(公告)号：US06218243B1

公开(公告)日：2001-04-17

申请号：US09252127

申请日：1999-02-18

申请人： Wayne Tan ,  Kun-Chi Lin ,  Gwo-Shii Yang

发明人： Wayne Tan ,  Kun-Chi Lin ,  Gwo-Shii Yang

IPC分类号： H01L218242

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： A method of fabricating a DRAM capacitor includes the step of forming an insulated layer and an etching stop layer successively on a substrate having a device structure. A contact window is formed within the etching stop layer and the insulated layer. A conductive layer is formed on the etching layer to fill in the contact window and patterned to serve as a lower electrode of the capacitor. A highly doped dielectric layer is then formed on the lower electrode and a thermal process is performed to diffuse the dopants inside the highly doped dielectric layer into the surface of the lower electrode. The dielectric layer is removed. A capacitor dielectric layer and an upper electrode are successively formed on the lower electrode to complete the fabrication of the capacitor.

摘要翻译： 制造DRAM电容器的方法包括在具有器件结构的衬底上依次形成绝缘层和蚀刻停止层的步骤。 在蚀刻停止层和绝缘层内形成接触窗。 在蚀刻层上形成导电层以填充接触窗口并图案化以用作电容器的下电极。 然后在下电极上形成高掺杂的电介质层，并进行热处理，以将高掺杂电介质层内的掺杂剂扩散到下电极的表面。 去除电介质层。 电容器电介质层和上电极依次形成在下电极上以完成电容器的制造。

公开(公告)号：US06200904B1

公开(公告)日：2001-03-13

申请号：US09323546

申请日：1999-06-01

申请人： Wayne Tan ,  Gwo-Shii Yang ,  Kun-Chi Lin

发明人： Wayne Tan ,  Gwo-Shii Yang ,  Kun-Chi Lin

IPC分类号： H01L21302

CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： The present invention relates to a method of forming a contact hole of a DRAM on the semiconductor wafer. The semiconductor wafer comprises a substrate, a first dielectric layer, two bit lines on the first dielectric layer, a second dielectric layer, and a photo-resist layer comprising an opening to define the pattern of the contact hole. The method comprises performing a first anisotropic etching process to vertically remove a portion of the two dielectric layers and two bit lines to grossly form the contact hole, removing the photo-resist layer in its entirety, performing a thermal oxidation to form a silicon oxide layer on the side walls of the two bit lines, then forming a silicon nitride layer on the surface of the contact hole, and performing a dry etching to remove the silicon nitride layer. There is a silicon oxide layer and a silicon nitride layer between the bit line and the contact hole, and the contact area of the contact hole will not be reduced.

摘要翻译： 本发明涉及在半导体晶片上形成DRAM的接触孔的方法。 半导体晶片包括基板，第一介电层，第一电介质层上的两个位线，第二电介质层和包含用于限定接触孔的图案的开口的光致抗蚀剂层。 该方法包括执行第一各向异性蚀刻工艺以垂直去除两个电介质层和两个位线的一部分，以大致形成接触孔，完全去除光致抗蚀剂层，进行热氧化以形成氧化硅层 在两个位线的侧壁上，然后在接触孔的表面上形成氮化硅层，并进行干蚀刻以除去氮化硅层。 位线和接触孔之间有一个氧化硅层和一个氮化硅层，接触孔的接触面积不会减小。

公开(公告)号：US6150278A

公开(公告)日：2000-11-21

申请号：US357236

申请日：1999-07-20

申请人： Wayne Tan ,  Kun-Chi Lin

发明人： Wayne Tan ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L27/10852 ,  H01L27/10885 ,  H01L28/84

摘要： An improved method of fabricating a node capacitor for a dynamic random access memory (DRAM) process is disclosed. The process includes depositing a first interpoly dielectric (IPD1) layer over a substrate, patterning a first photoresist layer on the first interpoly dielectric layer, thereby defining a trench. A trench is etched in the first interpoly dielectric layer using the first photoresist layer as a mask. A first polysilicon layer is deposited on the first interpoly dielectric layer. The first polysilicon layer is etched to expose the first interpoly dielectric layer, then forming a landing pad over the substrate. In order to a polycide layer and a second interpoly dielectric (IPD2) layer are deposited, patterning a second photoresist layer, thereby defining a bit line structure. A bit line structure is formed, then depositing a spacer on the bit line structure. A second polysilicon layer is deposited, patterning a third photoresist layer, thereby defining a bottom electrode. A bottom electrode is formed, then depositing a thin NO (silicon nitride-silicon oxide) dielectric layer on the bottom electrode. An addition step is performed before forming the thin NO dielectric layer on the bottom electrode. In this additional step, a hemispherical grain (HSG) polysilicon layer is formed on the second polysilicon layer. This advantage is used to the hemispherical grain polysilicon layer increasing the area of a node capacitor. A third polysilicon layer is deposited completely covering the thin NO dielectric layer to form a top electrode.

摘要翻译： 公开了一种制造用于动态随机存取存储器（DRAM）工艺的节点电容器的改进方法。 该方法包括在衬底上沉积第一层间电介质（IPD1）层，对第一层间电介质层上的第一光致抗蚀剂层进行构图，从而限定沟槽。 使用第一光致抗蚀剂层作为掩模，在第一互聚电介质层中蚀刻沟槽。 第一多晶硅层沉积在第一互聚电介质层上。 蚀刻第一多晶硅层以暴露第一多余介电层，然后在衬底上形成着色焊盘。 为了沉积多晶硅化物层和第二多晶硅电介质（IPD2）层，图案化第二光致抗蚀剂层，从而限定位线结构。 形成位线结构，然后在位线结构上沉积间隔物。 沉积第二多晶硅层，图案化第三光致抗蚀剂层，从而限定底部电极。 形成底部电极，然后在底部电极上沉​​积薄的NO（氮化硅 - 氧化硅）电介质层。 在底电极上形成薄的NO电介质层之前进行添加步骤。 在该附加步骤中，在第二多晶硅层上形成半球状晶粒（HSG）多晶硅层。 这个优点用于半球形晶粒多晶硅层增加节点电容器的面积。 沉积第三多晶硅层完全覆盖薄的NO介电层以形成顶部电极。

公开(公告)号：US6136642A

公开(公告)日：2000-10-24

申请号：US220146

申请日：1998-12-23

申请人： Wayne Tan ,  Kun-Chi Lin

发明人： Wayne Tan ,  Kun-Chi Lin

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10885 ,  H01L27/10814

摘要： A method of fabricating a dynamic random access memory includes forming a dummy layer over the isolation layer, in which the dummy layer has a higher etching selectivity than oxide. A dielectric layer is applied to isolate the bit lines. Then, a passivation layer is formed over the entire structure and a node contact opening is formed thereon. A liner oxide layer is then formed in the node contact opening to isolate the bit lines and the electrode of the capacitor. The node contact opening has a larger misalignment tolerance.

摘要翻译： 制造动态随机存取存储器的方法包括在隔离层上形成虚设层，其中虚设层具有比氧化物更高的蚀刻选择性。 施加电介质层以隔离位线。 然后，在整个结构上形成钝化层，并在其上形成节点接触开口。 然后在节点接触开口中形成衬垫氧化物层，以隔离电容器的位线和电极。 节点接触开口具有较大的不对准公差。

公开(公告)号：US6140168A

公开(公告)日：2000-10-31

申请号：US241330

申请日：1999-02-01

申请人： Wayne Tan ,  Kun-Chi Lin

发明人： Wayne Tan ,  Kun-Chi Lin

IPC分类号： H01L21/60 ,  H01L21/425

CPC分类号： H01L21/76897

摘要： A method of fabricating a self-aligned contact window includes forming an undoped dielectric layer on a substrate having a least gate structure. The dopants are implanted into a pre-determined region of the undoped dielectric layer and the dielectric layer with the dopants is then removed. A self-aligned contact is therefore completed.

摘要翻译： 制造自对准接触窗的方法包括在具有最小栅极结构的衬底上形成未掺杂的电介质层。 将掺杂剂注入到未掺杂介电层的预定区域中，然后除去具有掺杂剂的介电层。 因此，完成自对准的联系。

公开(公告)号：US06417065B1

公开(公告)日：2002-07-09

申请号：US09718190

申请日：2000-11-20

申请人： King-Lung Wu ,  Kun-Chi Lin

发明人： King-Lung Wu ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L27/10855 ,  H01L21/76802 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91

摘要： A method of fabricating a bottom electrode is described. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer. An isolation spacer remaining from the conformal isolation layer is formed on a sidewall of the contact node opening. A conformal conductive layer is formed in the opening and the node contact opening to make contact with the conductive plug. The third dielectric layer is removed.

摘要翻译： 描述制造底部电极的方法。 提供其中具有导电层的基板。 第一电介质层形成在衬底上。 导电插塞通过第一介电层形成，以与导电层电耦合。 在衬底上形成覆盖导电插塞的覆盖层。 在盖层上方形成隔离层。 多个位线形成在隔离层上。 在隔离层上形成第二电介质层。 通过第二介电层，位线和隔离层形成节点接触开口以露出盖层。 在衬底上形成保形隔离层以部分地填充接触节点开口。 在衬底上形成具有开口的第三电介质层。 开口与节点接触开口对齐。 执行蚀刻步骤以去除由开口和盖层暴露的一部分共形隔离层。 从保形隔离层剩余的隔离间隔物形成在接触节点开口的侧壁上。 在开口和节点接触开口中形成共形导电层以与导电插塞接触。 去除第三电介质层。

公开(公告)号：US06225160B1

公开(公告)日：2001-05-01

申请号：US09295067

申请日：1999-04-20

申请人： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

发明人： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

IPC分类号： H01L218242

CPC分类号： H01L28/60 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

摘要： A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

摘要翻译： 一种制造电容器的底部电极的方法。 在基板上形成第一电介质层。 在第一电介质层上形成覆盖层。 在盖层上形成第二电介质层。 形成节点接触孔以穿透第二介电层，盖层和第一介电层。 衬垫层形成在节点接触孔的侧壁上。 在第二电介质层上形成限制层。 在限制层的一部分上形成有图案的导电层，并填充节点接触孔。 在图案化的导电层上形成选择性半球形纹理层。

公开(公告)号：US6150223A

公开(公告)日：2000-11-21

申请号：US287881

申请日：1999-04-07

申请人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

发明人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

IPC分类号： H01L21/60 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/76897 ,  H01L21/823468

摘要： A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate. Removing the first photoresist layer and the fourth dielectric layer of the interior circuit, a fifth dielectric layer is formed on the third dielectric layer of the interior circuit. The fourth dielectric layer and the top surface of the second dielectric layer of the peripheral circuit are removed. The fifth dielectric layer is formed on the first dielectric layer and the third peripheral of the peripheral circuit, and then the second photoresist layer on the fifth dielectric layer, wherein the third photoresist layer is patterned as a bit-line contact via of the interior circuit and the bit-line contact vias of the peripheral circuit. Finally, anisotropically etching the third photoresist layer and the fifth dielectric layer, a bit-line to the substrate contact via and a bit-line to the gate contact via are formed inside the fifth dielectric layer.

摘要翻译： 公开了一种用于形成不同宽度的栅极间隔物的方法。 该方法包括首先在半导体衬底上形成栅氧化层。 在栅极氧化物层上依次形成多晶硅层，导电层，第一介电层。 使用它们作为内部栅极和外围栅极进一步蚀刻第一介电层，导电层，多晶硅层和栅极氧化物层。 接下来，在内部栅极和外围栅极上形成第二电介质层，第三电介质层和第四电介质层，并且第一光致抗蚀剂层邻接内部电路的第四电介质层的表面。 此外，蚀刻外围栅极的第四介电层以形成外围栅极的第二间隔物，并且蚀刻外围栅极的第三介电层以形成外围栅极的第一间隔物。 去除内部电路的第一光致抗蚀剂层和第四电介质层，在内部电路的第三电介质层上形成第五电介质层。 除去第四电介质层和外围电路的第二电介质层的顶表面。 第五电介质层形成在第一电介质层和外围电路的第三外围，然后形成在第五介电层上的第二光致抗蚀剂层，其中第三光致抗蚀剂层被图案化为内部电路的位线接触通孔 和外围电路的位线接触通孔。 最后，在第五介电层内形成各向异性蚀刻第三光致抗蚀剂层和第五电介质层，到基板接触通孔的位线和到栅极接触通孔的位线。

公开(公告)号：US06124161A

公开(公告)日：2000-09-26

申请号：US203022

申请日：1998-12-01

申请人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

发明人： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/8234

CPC分类号： H01L28/84 ,  H01L27/10852

摘要： A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

摘要翻译： 提供了一种在多晶硅电极上形成半球形硅晶粒（HSG）层的方法。 该方法适合于在衬底上具有介电层的衬底，其具有用于暴露衬底的开口，并且在衬底上形成多晶硅层。 除了开口区域之外，在介电层上除去多晶硅层的一部分。 多晶硅层的每个侧壁都是倾斜的，从而形成梯形多晶硅基底。 缓冲层形成在梯形多晶硅基底上。 执行离子注入工艺以在梯形多晶硅基底的顶表面区域上形成具有足够深度的非晶硅层。 缓冲层包括氧化硅或氮化硅。 在离子注入期间，也可以将氧或氮元素轰击到非晶硅层中，以缓冲非晶硅层再结晶。 在梯形多晶硅电极基体上形成选择性HSG层。

公开(公告)号：US20100157627A1

公开(公告)日：2010-06-24

申请号：US12390309

申请日：2009-02-20

申请人： Kuan-Sheng Wang ,  Kun-Chi Lin ,  Ying-Chieh Wang ,  Shu-Hao Chang

发明人： Kuan-Sheng Wang ,  Kun-Chi Lin ,  Ying-Chieh Wang ,  Shu-Hao Chang

IPC分类号： H02M3/22 ,  G05F1/10 ,  G05F1/00

CPC分类号： G01R19/0084

摘要： An output voltage detecting circuit includes a conducting structure, a voltage regulator, a first resistor and a second resistor. The conducting structure includes a power output return terminal, a first contact and a second contact. A compensating voltage is generated between the first and second contacts when an output current flows through the first and second contacts. The voltage regulator adjusts a first current according to a voltage across a first circuit terminal and the ground terminal of the voltage regulator, thereby generating a detecting signal according to the first current. An output voltage across the positive power output terminal and the power output return terminal is subject to voltage division by the first and second resistors to generate a divided voltage. The voltage across the first circuit terminal and the ground terminal of the voltage regulator is equal to a difference between the divided voltage and the compensating voltage.

摘要翻译： 输出电压检测电路包括导电结构，电压调节器，第一电阻器和第二电阻器。 导电结构包括电源输出返回端子，第一触点和第二触点。 当输出电流流过第一和第二触点时，在第一和第二触点之间产生补偿电压。 电压调节器根据第一电路端子和电压调节器的接地端子之间的电压来调节第一电流，从而根据第一电流产生检测信号。 正功率输出端子和功率输出返回端子两端的输出电压经受第一和第二电阻器的分压以产生分压。 电压调节器的第一电路端子和接地端子之间的电压等于分压和补偿电压之间的差值。