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11.发明授权公开(公告)号：US09524934B2
公开(公告)日：2016-12-20
申请号：US13302335
申请日：2011-11-22
IPC分类号： H01L21/8238 , H01L23/525 , H01L27/06 , H01L29/51 , H01L29/66
CPC分类号： H01L23/5256 , H01L21/823437 , H01L27/0617 , H01L27/0629 , H01L27/11206 , H01L29/4966 , H01L29/517 , H01L29/66545 , H01L2924/0002 , H01L2924/00
摘要： A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
摘要翻译： 形成集成电路的方法包括在衬底上形成至少一个晶体管。 形成至少一个晶体管包括在衬底上形成栅极电介质结构。 在栅介电结构上形成功函数金属层。 在功函数金属层上形成导电层。 源极/漏极（S / D）区域形成为与栅极电介质结构的每个侧壁相邻。 在衬底上形成至少一个电熔丝。 形成至少一个电熔丝包括在衬底上形成第一半导体层。 在第一半导体层上形成第一硅化物层。
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公开(公告)号：US09001613B2
公开(公告)日：2015-04-07
申请号：US13397415
申请日：2012-02-15
申请人： Bing Wang , Kuoyuan (Peter) Hsu
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C8/18 , G11C7/18 , G11C7/22 , G11C11/419
CPC分类号： G11C7/18 , G11C7/227 , G11C11/419
摘要： A tracking circuit in a memory macro includes a data line, a first tracking cell, and a plurality of transistors. The first tracking cell is electrically coupled to the data line. The plurality of transistors is electrically coupled to the data line. The plurality of transistors is configured to cause a delay on a transition of a signal of the data line based on a delay current. The signal of the data line is configured for use in generating a signal of a control line of a memory cell of the memory macro.
摘要翻译： 存储器宏中的跟踪电路包括数据线，第一跟踪单元和多个晶体管。 第一跟踪单元电耦合到数据线。 多个晶体管电耦合到数据线。 多个晶体管被配置为基于延迟电流在数据线的信号的转变上引起延迟。 数据线的信号被配置为用于产生存储器宏的存储单元的控制线的信号。
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公开(公告)号：US08947949B2
公开(公告)日：2015-02-03
申请号：US13099809
申请日：2011-05-03
申请人： Bing Wang , Kuoyuan (Peter) Hsu
发明人： Bing Wang , Kuoyuan (Peter) Hsu
IPC分类号： G11C7/00 , G11C11/417
CPC分类号： G11C11/417 , G11C2207/2227
摘要： A circuit includes a memory cell having a ground reference node, a switch coupled to the ground reference node, and a mode changing circuit having an output coupled to the switch. The mode changing circuit is configured to change a logic state of the output between a first output logic state and a second output logic state in response to a change in an operational voltage and/or temperature, thereby set the memory cell in a first mode in which the ground reference node is at first reference level or in a second mode in which the ground reference node is at a second reference level different from the first reference level.
摘要翻译： 电路包括具有接地参考节点的存储器单元，耦合到接地参考节点的开关，以及具有耦合到开关的输出的模式改变电路。 模式改变电路被配置为响应于操作电压和/或温度的变化而改变第一输出逻辑状态和第二输出逻辑状态之间的输出的逻辑状态，从而将存储器单元设置为第一模式 其中地面参考节点处于第一参考水平或第二模式，其中地面参考节点处于与第一参考水平不同的第二参考水平。
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公开(公告)号：US08400860B2
公开(公告)日：2013-03-19
申请号：US12839542
申请日：2010-07-20
IPC分类号： G11C17/16
CPC分类号： G11C17/16
摘要： Some embodiments regard a memory array that has a plurality of rows and columns. A column includes a program control device, a plurality of eFuse memory cells in the column, a sense amplifier, and a bit line coupling the program control device, the plurality of memory cells in the column, and the sense amplifier. A row includes a plurality of eFuse memory cells in the row, a word line coupling the plurality of eFuse memory cells in the row, and a footer configured as a current path for the plurality of eFuse memory cells in the row.
摘要翻译： 一些实施例涉及具有多个行和列的存储器阵列。 列包括程序控制装置，列中的多个eFuse存储器单元，读出放大器和耦合程序控制装置，列中的多个存储单元和读出放大器的位线。 行包括行中的多个eFuse存储器单元，耦合行中的多个eFuse存储器单元的字线和被配置为行中的多个eFuse存储器单元的当前路径的页脚。
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公开(公告)号：US08194490B2
公开(公告)日：2012-06-05
申请号：US12877646
申请日：2010-09-08
IPC分类号： G11C17/18
CPC分类号： G11C17/165
摘要： Some embodiments regard a memory array that has a plurality of eFuse memory cells arranged in rows and columns, a plurality of bit lines, and a plurality of word lines. A column includes a bit line selector, a bit line coupled to the bit line selector, and a plurality of eFuse memory cells. An eFuse memory cell of the column includes a PMOS transistor and an eFuse. A drain of the PMOS transistor is coupled to a first end of the eFuse. A gate of the PMOS transistor is coupled to a word line. A source of the PMOS transistor is coupled to the bit line of the column.
摘要翻译： 一些实施例涉及具有以行和列，多个位线和多个字线布置的多个eFuse存储器单元的存储器阵列。 列包括位线选择器，耦合到位线选择器的位线和多个eFuse存储器单元。 该列的eFuse存储单元包括PMOS晶体管和eFuse。 PMOS晶体管的漏极耦合到eFuse的第一端。 PMOS晶体管的栅极耦合到字线。 PMOS晶体管的源极耦合到列的位线。
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公开(公告)号：US07733724B2
公开(公告)日：2010-06-08
申请号：US11970188
申请日：2008-01-07
申请人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
发明人： Kuoyuan (Peter) Hsu , Bing Wang , Young Suk Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/1048
摘要： A method of operating a memory includes performing a write operation and a read operation on a memory cell. The write operation includes starting a first global bit line (GBL) pre-charge on a GBL; and after the first GBL pre-charge is started, enabling a word line to write into the memory cell, wherein the steps of starting the first GBL pre-charge and enabling the word line have a first time interval. The read operation includes starting a second GBL pre-charge on the GBL; and after the second GBL pre-charge is started, enabling the word line to read from the memory cell, wherein the steps of starting the second GBL pre-charge and enabling the word line have a second time interval. The first time interval is greater than the second time interval.
摘要翻译： 操作存储器的方法包括对存储器单元执行写入操作和读取操作。 写入操作包括在GBL上启动第一个全局位线（GBL）预充电; 并且在开始第一GBL预充电之后，使得字线能够写入存储单元，其中启动第一GBL预充电和启用字线的步骤具有第一时间间隔。 读取操作包括在GBL上启动第二个GBL预充电; 并且在开始第二GBL预充电之后，使得字线能够从存储器单元读取，其中启动第二GBL预充电和使字线的步骤具有第二时间间隔。 第一时间间隔大于第二时间间隔。
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公开(公告)号：US20090058511A1
公开(公告)日：2009-03-05
申请号：US11845628
申请日：2007-08-27
申请人： Kuoyuan (Peter) Hsu , Maofeng Lan
发明人： Kuoyuan (Peter) Hsu , Maofeng Lan
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A system and a method is disclosed for allowing bandgap circuitry to function on a low supply voltage integrated circuit, and for using the reference voltage (Vbg) generated by the bandgap circuitry to enable a reference voltage to control system voltage. An illustrative embodiment comprises a charge pump to raise a supply voltage to a system voltage, and an open loop controller, which provides a first signal to activate the charge pump, enabling a bandgap circuit, which outputs a bandgap voltage reference. Further, the system comprises a closed loop controller, which regulates the system voltage by comparing the system voltage to the bandgap reference voltage. Upon the system voltage falling below a target voltage, the closed loop controller provides a second signal to activate the charge pump. Additionally the system comprises a switch controller, which selects the closed loop controller upon sensing the bandgap circuit is active.
摘要翻译： 公开了一种用于允许带隙电路在低电源电压集成电路上工作并且使用由带隙电路产生的参考电压（Vbg）使得参考电压能够控制系统电压的系统和方法。 示例性实施例包括用于提高系统电压的电源电压的电荷泵和提供第一信号以激活电荷泵的开环控制器，其实现输出带隙电压基准的带隙电路。 此外，该系统包括闭环控制器，其通过将系统电压与带隙参考电压进行比较来调节系统电压。 当系统电压低于目标电压时，闭环控制器提供第二信号以激活电荷泵。 另外，该系统包括开关控制器，其在感测带隙电路有效时选择闭环控制器。
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18.发明授权Integrated circuit structure to resolve deep-well plasma charging problem and method of forming the same 有权集成电路结构解决深井等离子体充电问题及其形成方法公开(公告)号：US08946825B2
公开(公告)日：2015-02-03
申请号：US13433194
申请日：2012-03-28
申请人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： David Yen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： H01L23/62
CPC分类号： H01L27/0928 , H01L21/263 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L27/0629 , H01L29/6609
摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.
摘要翻译： 在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。 反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。
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公开(公告)号：US08767498B2
公开(公告)日：2014-07-01
申请号：US13285357
申请日：2011-10-31
IPC分类号： G11C17/14
摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.
摘要翻译： 电路包括熔丝电路和控制电路。 保险丝电路具有电熔丝。 控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。
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公开(公告)号：US08704376B2
公开(公告)日：2014-04-22
申请号：US13443467
申请日：2012-04-10
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译： 布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。 井在底层。 第一多晶硅区位于第一掺杂区和第二掺杂区之间。 第二聚合区位于第三掺杂区和第四掺杂区之间。 第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。 第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。 阱被配置为用作晶体管的体积并从第二电源接收第二电压值。
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