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    DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT
    13.
    发明申请
    DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路的数据接收器

    公开(公告)号：US20090128214A1

    公开(公告)日：2009-05-21

    申请号：US12177023

    申请日：2008-07-21

    申请人： Hyung Soo Kim ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Hyung Soo Kim ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： H03L5/00

    CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/1087

    摘要： A data receiver includes a plurality of amplifiers for receiving data in response to clock signals having a predetermined phase difference, and amplifying the received data by performing an equalization function based on feedback data, thereby outputting amplification signals, and a plurality of latches for latching output of the amplifiers, respectively. One amplifier receives the amplification signal, as feedback data, from another amplifier receiving a clock signal having a phase more advanced than a phase of a clock signal received in the one amplifier.

    摘要翻译： 数据接收机包括响应于具有预定相位差的时钟信号而接收数据的多个放大器，并且通过基于反馈数据执行均衡功能来放大接收数据，从而输出放大信号，以及多个锁存器用于锁存输出 的放大器。 一个放大器接收作为反馈数据的放大信号，来自另一个放大器接收时钟信号，该时钟信号的相位比在一个放大器中接收的时钟信号的相位更先进。

    DLL circuit of semiconductor memory apparatus
    18.
    发明授权
    DLL circuit of semiconductor memory apparatus 有权
    半导体存储装置的DLL电路

    公开(公告)号：US07948287B2

    公开(公告)日：2011-05-24

    申请号：US11964824

    申请日：2007-12-27

    申请人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

    发明人： Ic Su Oh ,  Kun Woo Park ,  Yong Ju Kim ,  Jong Woon Kim ,  Hee Wong Song ,  Hyung Soo Kim ,  Tae Jin Hwang

    IPC分类号： H03L7/06

    CPC分类号： G11C7/22 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

    摘要： A DLL circuit for a semiconductor memory apparatus includes a delay line having a coarse delay chain, which has a plurality of coarse delayers connected in series and is inputted with a reference clock signal, and a plurality of fine delayers which receive output clock signals of the respective coarse delayers, and a delay control section for comparing phases of an output clock signal of a final coarse delayer among the coarse delayers with the reference clock signal and generating coarse control signals for controlling the coarse delayers and for comparing phases of an output clock signal of a fine delayer inputted with the output clock signals of the final coarse delayer, as a fine feedback clock signal, with the reference clock signal and generating fine control signals for controlling the fine delayers.

    摘要翻译： 一种用于半导体存储装置的DLL电路包括具有粗略延迟链的延迟线，该延迟线具有串联连接并被输入参考时钟信号的多个粗延迟器，以及多个精细延迟器，其接收输出时钟信号的输出时钟信号 相应的粗延迟器和延迟控制部分，用于将粗延迟器中的最终粗延迟器的输出时钟信号的相位与参考时钟信号进行比较，并产生用于控制粗略延迟器的粗略控制信号，并用于比较输出时钟信号的相位 输入与最终粗略延迟器的输出时钟信号作为精细反馈时钟信号的精细延迟器与参考时钟信号，并产生用于控制精细延迟器的精细控制信号。