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    Multi-level enumerative encoder and decoder
    11.
    发明授权
    Multi-level enumerative encoder and decoder 有权
    多级枚举编码器和解码器

    公开(公告)号：US09251845B2

    公开(公告)日：2016-02-02

    申请号：US14318665

    申请日：2014-06-29

    Applicant: LSI Corporation

    Inventor： Victor Krachkovsky ,  Razmik Karabed ,  Shaohua Yang ,  Wu Chang

    IPC: G11B5/02 ,  G11B20/12

    CPC classification number: G11B20/1217 ,  G11B20/1833 ,  H03M7/4006 ,  H03M13/1102

    Abstract: A storage system includes a storage medium operable to maintain a data set, a read/write head assembly operable to write the data set to the storage medium and to read the data set from the storage medium, a multi-level enumerative encoder operable to encode the data set before it is written to the storage medium as encoded data, wherein the enumerative encoder applies an enumeration using a plurality of level-dependent bases, and a decoder operable to decode the data set after it is read from the storage medium.

    Abstract translation: 存储系统包括可操作以保持数据集的存储介质，可操作以将数据集写入存储介质并从存储介质读取数据集的读/写头组件，可操作以编码的多级枚举编码器 其前的数据集作为编码数据被写入存储介质，其中该枚举编码器使用多个依赖于水平的基站来应用枚举，以及解码器，用于在从存储介质读取数据集之后对其进行解码。

    Pattern-dependent short media defect detection
    13.
    发明授权
    Pattern-dependent short media defect detection 有权
    模式依赖的短介质缺陷检测

    公开(公告)号：US09026876B2

    公开(公告)日：2015-05-05

    申请号：US13631075

    申请日：2012-09-28

    Applicant: LSI Corporation

    Inventor： Fan Zhang ,  Wu Chang

    IPC: H03M13/00 ,  G06F11/00

    CPC classification number: G06F11/00 ,  H03M13/1102 ,  H03M13/3723 ,  H03M13/6337 ,  H04L1/005

    Abstract: Systems and methods for computing sign disagreement between signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector; and detecting one or more consecutive sign disagreements between an extrinsic output of a detector and an extrinsic output of a decoder.

    Abstract translation: 用于计算信号之间的符号不一致的系统和方法可以实现一个或多个操作，包括但不限于：接收外在对数似然比（LLR）值; 根据外在LLR值和先验LLR值之间的符号不一致，增加符号不一致计数器; 提供二进制短介质缺陷（SMD）检测器的符号不一致计数器的值; 以及检测检测器的外部输出和解码器的非本征输出之间的一个或多个连续符号不一致。

    Multi-level run-length limited finite state machine for magnetic recording channel
    14.
    发明授权
    Multi-level run-length limited finite state machine for magnetic recording channel 有权
    用于磁记录通道的多级游程限制有限状态机

    公开(公告)号：US08854755B2

    公开(公告)日：2014-10-07

    申请号：US13654893

    申请日：2012-10-18

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Razmik Karabed ,  Shaohua Yang ,  Fan Zhang

    IPC: G11B20/10 ,  G11B5/00 ,  G06F11/16 ,  G11B5/02

    CPC classification number: G11B5/02 ,  G06F11/16 ,  G11B20/10277

    Abstract: A system is described for constructing maximum transition run modulation code based upon a multi-level run-length limited finite state machine. A processor is configured to receive information from a hard disk drive via a read channel and recover data from the hard disk drive using maximum transition run modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct a maximum transition run modulation code to mimic the optimized Markov source based upon a finite state machine having a limited transition run length and a multi-level periodic structure.

    Abstract translation: 描述了一种基于多级游程限制有限状态机来构建最大过渡运行调制码的系统。 处理器被配置为经由读取通道从硬盘驱动器接收信息，并使用最大过渡运行调制码从硬盘驱动器恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化马尔可夫源，并且构建最大过渡运行调制码 基于具有有限转换行程长度和多级周期性结构的有限状态机模拟优化的马尔可夫源。

    PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION
    17.
    发明申请
    PATTERN-DEPENDENT SHORT MEDIA DEFECT DETECTION 有权
    模式相关短缺媒体缺陷检测

    公开(公告)号：US20140095963A1

    公开(公告)日：2014-04-03

    申请号：US13631075

    申请日：2012-09-28

    Applicant: LSI CORPORATION

    Inventor： Fan Zhang ,  Wu Chang

    IPC: G06F11/00 ,  G06F7/04

    CPC classification number: G06F11/00 ,  H03M13/1102 ,  H03M13/3723 ,  H03M13/6337 ,  H04L1/005

    Abstract: Systems and methods for computing sign disagreement between Le and La signals may implement one or more operations including, but not limited to: receiving an extrinsic log likelihood ratio (LLR) value; incrementing a sign-disagreement counter according to a sign disagreement between the extrinsic LLR value and an a priori LLR value; providing a value of the sign-disagreement counter to a binary short media defect (SMD) detector.

    Abstract translation: 用于计算Le和La信号之间符号不一致的系统和方法可以实现一个或多个操作，包括但不限于：接收外在对数似然比（LLR）值; 根据外在LLR值和先验LLR值之间的符号不一致，增加符号不一致计数器; 提供二进制短介质缺陷（SMD）检测器的符号分歧计数器的值。

    Detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window
    18.
    发明授权
    Detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window 有权
    在滑动窗口内的多个位的误差相关的闪速存储器中进行检测和解码

    公开(公告)号：US09082480B2

    公开(公告)日：2015-07-14

    申请号：US13780203

    申请日：2013-02-28

    Applicant: LSI Corporation

    Inventor： Adbel Hakim S. Alhussien ,  Wu Chang ,  Erich F. Haratsch ,  Ming Jin

    IPC: G11C11/34 ,  G11C16/04 ,  G11C11/56

    CPC classification number: G11C16/04 ,  G11C11/5642

    Abstract: Methods and apparatus are provided for detection and decoding in flash memories with error correlations for a plurality of bits within a sliding window. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and decoding the plurality of bits using a binary decoder. The non-binary log likelihood ratio captures one or more of intra-page correlations and/or intra-cell correlations. A least significant bit and a most significant bit of a given cell can be independently converted and/or jointly converted to the non-binary log likelihood ratio.

    Abstract translation: 提供了用于在闪速存储器中进行检测和解码的方法和装置，其具有滑动窗口内的多个位的误差相关性。 来自闪存设备的数据通过从闪存设备的一个或多个页面获得多个位的一个或多个读取值来处理; 基于当从多个比特读取特定模式时将给定数据模式写入多个比特的概率，将多个比特的一个或多个读取值转换为非二进制对数似然比; 以及使用二进制解码器对所述多个比特进行解码。 非二进制对数似然比捕获页内相关和/或小区内相关中的一个或多个。 给定单元的最低有效位和最高有效位可以独立地转换和/或共同转换为非二进制对数似然比。

    Multi-level run-length limited finite state machine with multi-penalty
    20.
    发明授权
    Multi-level run-length limited finite state machine with multi-penalty 有权
    多级游程限制有限状态机多罚

    公开(公告)号：US08792195B2

    公开(公告)日：2014-07-29

    申请号：US13654931

    申请日：2012-10-18

    Applicant: LSI Corporation

    Inventor： Wu Chang ,  Razmik Karabed ,  Fan Zhang

    IPC: G11B5/00 ,  G11B20/18 ,  G11B20/24

    CPC classification number: G11B20/1833 ,  G11B20/10277 ,  G11B20/10287

    Abstract: Techniques are described for constructing maximum transition run (MTR) modulation code based upon a multi-level (ML) run-length limited (RLL) finite state machine (FSM) that implements different sets of penalties. A processor is configured to receive information from a hard disk drive (HDD) via a read channel and recover data from the HDD using MTR modulation code. A memory has computer executable instructions configured for execution by the processor to model a magnetic recording channel as a partial response channel, model a source of information to the magnetic recording channel to provide an optimized Markov source, and construct an MTR modulation code to mimic the optimized Markov source based upon an FSM having a limited transition run length and a multi-level periodic structure. The FSM provides at least two different sets of penalties in a period.

    Abstract translation: 描述了基于实现不同处罚集的多级（ML）游程限制（RLL）有限状态机（FSM）来构建最大过渡运行（MTR）调制码的技术。 处理器被配置为经由读通道从硬盘驱动器（HDD）接收信息，并且使用MTR调制码从HDD恢复数据。 存储器具有被配置为由处理器执行以将磁记录通道建模为部分响应通道的计算机可执行指令，将信息源建模到磁记录通道以提供优化的马尔可夫源，并构建MTR调制码以模拟 基于具有有限转换行程长度和多级周期结构的FSM的优化马尔可夫源。 FSM在一段时间内至少提供两套不同的罚则。

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