公开(公告)号：US20140268400A1

公开(公告)日：2014-09-18

申请号：US13800370

申请日：2013-03-13

Applicant: LSI CORPORATION

Inventor： Jianzhong Huang ,  Yu Kou ,  Haitao Xia ,  Seongwook Jeong

IPC: H03M13/05 ,  H03M13/41 ,  G11B20/10

CPC classification number: H03M13/41 ,  G11B5/035 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10268 ,  G11B2005/0013 ,  H03M13/13 ,  H03M13/6343

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for performing loop feedback in a data processing system.

Abstract translation: 本发明涉及用于数据处理的系统和方法，更具体地涉及用于在数据处理系统中执行循环反馈的系统和方法。

公开(公告)号：US20140362463A1

公开(公告)日：2014-12-11

申请号：US13941464

申请日：2013-07-13

Applicant: LSI Corporation

Inventor： Bruce Wilson ,  Yang Han ,  Yu Kou ,  Rui Cao

IPC: G11B20/14 ,  G11B5/09

CPC classification number: G11B5/09 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/1403 ,  G11B2220/2516

Abstract: Aspects of the disclosure pertain to an apparatus for detecting timing errors including an analog to digital converter circuit, a diversity loop detector and a timing error calculation circuit. The analog to digital converter circuit is operable to convert an input signal into a series of digital samples. The diversity loop detector is operable to apply a data detection algorithm to a plurality of signals derived from the series of digital samples at different phase offsets, to select one of the phase offsets, and to yield a detected output with the selected phase offset. The timing error calculation circuit is operable to calculate a timing error of the analog to digital converter circuit based at least in part on the selected phase offset.

Abstract translation: 本公开的方面涉及用于检测定时误差的装置，包括模数转换器电路，分集环路检测器和定时误差计算电路。 模数转换器电路可操作以将输入信号转换为一系列数字采样。 分集环路检测器可操作以将数据检测算法应用于在不同相位偏移处从一系列数字样本导出的多个信号，以选择相位偏移中的一个，并产生具有所选相位偏移的检测输出。 定时误差计算电路可用于至少部分地基于所选择的相位偏移来计算模数转换器电路的定时误差。

公开(公告)号：US20140281790A1

公开(公告)日：2014-09-18

申请号：US13912079

申请日：2013-06-06

Applicant: LSI Corporation

Inventor： Zongwang Li ,  Yu Kou ,  Chung-Li Wang ,  Shaohua Yang ,  Shu Li

IPC: H03M13/29

CPC classification number: H03M13/1171 ,  H03M13/611 ,  H03M13/616

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to systems and methods for multi-stage encoding for concatenated low density parity check codes.

Abstract translation: 用于数据处理的系统，方法，设备，电路，更具体地涉及用于级联低密度奇偶校验码的多级编码的系统和方法。

公开(公告)号：US08837263B1

公开(公告)日：2014-09-16

申请号：US13850942

申请日：2013-03-26

Applicant: LSI Corporation

Inventor： Rui Cao ,  Haitao Xia ,  Yu Kou

IPC: G11B20/20 ,  G11B27/30

CPC classification number: G11B27/3027 ,  G11B20/10 ,  G11B20/1403 ,  G11B27/10

Abstract: A hard disk drive includes a processor to automatically adjust a threshold level for finding sync-marks. The processor determines all possible sync-mark patterns for a particular pattern length and analyzes each pattern with reference to real world data. The pattern with the largest distance gap is used. The threshold level is then adjusted dynamically to produce the lowest possible failure rate for the given pattern.

Abstract translation: 硬盘驱动器包括一个处理器，用于自动调整阈值水平以查找同步标记。 处理器确定特定图案长度的所有可能的同步标记图案，并参考真实世界数据分析每个图案。 使用距离最大的图案。 然后动态调整阈值电平，以产生给定模式的最低可能故障率。

公开(公告)号：US08773799B1

公开(公告)日：2014-07-08

申请号：US13724946

申请日：2012-12-21

Applicant: LSI Corporation

Inventor： Suharli Tedja ,  Shaohua Yang ,  Fan Zhang ,  Qi Zuo ,  Joseph Garofalo ,  Yu Kou

IPC: G11B5/09

CPC classification number: G06F1/06 ,  G06F1/08 ,  G06F1/206

Abstract: An apparatus comprises read channel circuitry and associated signal processing circuitry comprising frontend processing circuitry and backend processing circuitry. The frontend processing circuitry comprises a loop detector and equalizer configured to determine an equalized read channel signal from a read channel signal and a decoding module configured to apply verification and scrambling processing on a decoded read channel signal. The backend processing circuitry comprises a backend detector, an interleaver, a backend decoder, and a de-interleaver configured to perform an iterative decoding process on the equalized read channel signal to determine the decoded read channel signal. The frontend processing circuitry is controlled by a first clock having an associated first clock rate and the backend processing circuitry is controlled by a selected one of the first clock and a second clock having an associated second clock rate determined at least in part by the first clock rate and a maximum clock rate.

Abstract translation: 一种装置包括读通道电路和包括前端处理电路和后端处理电路的相关信号处理电路。 前端处理电路包括环路检测器和均衡器，其被配置为从读取信道信号确定均衡的读取信道信号，以及解码模块，被配置为对解码的读取信道信号进行验证和加扰处理。 后端处理电路包括后端检测器，交织器，后端解码器和解交织器，被配置为对均衡的读信道信号执行迭代解码处理，以确定解码的读信道信号。 前端处理电路由具有相关联的第一时钟速率的第一时钟控制，并且后端处理电路由第一时钟中所选择的一个控制，第二时钟具有至少部分地由第一时钟确定的相关联的第二时钟速率 速率和最大时钟速率。