公开(公告)号：US5282169A

公开(公告)日：1994-01-25

申请号：US791973

申请日：1991-11-13

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C11/413

CPC分类号： G11C16/28

摘要： The sense circuit recognizes the virgin or programmed status of cells in storage devices (e.g. non-volatile memories of the type with unbalanced loads), and includes a sense amplifier (SA) having a first input (Y) connected to a number of selectable virgin reference cells (T.sub.vr1, T.sub.vr2) and a second input (X) connected to a number of selectable matrix cells (T.sub.vm, T.sub.pm). According to the invention, the current path of a compensatory programmed cell (NP) is connected between a reference voltage and the first input (Y) of the sense amplifier (SA), with the gate of the compensatory programmed cell being connected to a voltage source (Vs) which selects the compensatory programmed cell at least while the sense amplifier reads a selected matrix cell.

摘要翻译： 感测电路识别存储设备（例如具有不平衡负载的类型的非易失性存储器）中的单元的原始或编程状态，并且包括具有连接到多个可选择处女的第一输入（Y）的读出放大器（SA） 参考单元（Tvr1，Tvr2）和连接到多个可选矩阵单元（Tvm，Tpm）的第二输入端（X）。 根据本发明，补偿编程单元（NP）的电流路径连接在参考电压和读出放大器（SA）的第一输入端（Y）之间，补偿编程单元的栅极连接到电压 源（Vs）至少在读出放大器读取所选择的矩阵单元时选择补偿编程单元。

公开(公告)号：US5218570A

公开(公告)日：1993-06-08

申请号：US657083

申请日：1991-02-19

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C11/419 ,  G11C16/06 ,  G11C16/28 ,  G11C17/00 ,  G11C17/18

CPC分类号： G11C16/28

摘要： A sense circuit for reading EPROM and ROM type memory cells employs a circuit for generating an offsetting current which is exempt of error during transients and which thus permits to achieve a reduced access time. On the other hand, the sense circuit maintains the intrinsic advantages of a current-offset sensing architecture which is represented by a substantially unlimited operating voltage range toward the maximum value VCC.sub.max. The current generating circuit is driven by means of a supplementary row of cells which is decoded at every reading and which replicates, during transients, the behaviour of the row selected for the reading.

公开(公告)号：US5097226A

公开(公告)日：1992-03-17

申请号：US655049

申请日：1991-02-14

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： H03K3/354 ,  H02M3/07

CPC分类号： H02M3/073 ,  Y10S331/03

摘要： A voltage-boosted phase oscillator for driving a voltage multiplier comprises two intermeshed ring oscillators, each composed by an odd number of inverters connected in cascade through a closed loop and generating a normal phase and a voltage-boosted phase derived from the normal phase through a bootstrap circuit. The frequency of oscillation of both intermeshed ring oscillators is established by means of two similar RC networks common to both loops. The synchronization of the respective oscillations of the two rings is ensured by means of a plurality of SR flip-flops connected in cascade, formed by two NAND gates which, singularly, constitute as many inverters of the two rings. The oscillation and the arresting of the oscillation are controlled by means of a logic signal fed to a common input of a first pair of NAND gates which constitute respectively a first inverter of the relative ring oscillator and to a second input of which the phase produced by the relative ring oscillator is fed.

公开(公告)号：US5663921A

公开(公告)日：1997-09-02

申请号：US391159

申请日：1995-02-21

申请人： Luigi Pascucci ,  Marco Olivo ,  Carla Maris Golla

发明人： Luigi Pascucci ,  Marco Olivo ,  Carla Maris Golla

IPC分类号： G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32

CPC分类号： G11C7/22 ,  G11C16/32

摘要： A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.

摘要翻译： 电路产生灵活的时序，允许缓慢或快速的总体定时配置，以及通过提供两个（短或长）持续时间级别的预充电和检测间隔的两种配置。 为此，该电路包括一个可变的不对称传播线，该可变不对称传播线由基于存储的逻辑信号启用或禁用的一系列基本延迟元件组成，其状态在调试其中实施电路的存储器时被确定。

公开(公告)号：US5602786A

公开(公告)日：1997-02-11

申请号：US389599

申请日：1995-02-16

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/789

摘要： A method for programming redundancy registers in a column redundancy integrated circuitry for a semiconductor memory device with columns of memory elements grouped together to form portions of a bi-dimensional array of memory elements. The column redundancy circuitry comprises a plurality of non-volatile memory registers wherein each register is associated with a respective redundancy column of redundancy memory elements and each register is programmable to store an address of a defective column and an identifying code for identifying the portion of the bi-dimensional array to which the defective column belongs. When being programmed, each non-volatile memory register is supplied with column address signals and with a first subset of row address signals. The column address signals carry the address of a defective column and the first subset of row address signals carry the identifying code. One signal of a second subset of the row address signals is used to select one non-volatile memory register among the plurality of registers such that the defective column address and the identifying code carried by the column address signals and by the first subset of the row address signals are programmed into the selected non-volatile memory register. Using existing column and row address lines to program the redundancy memory registers reduces the need to generate dedicated on-chip signals, thereby minimizing the size of the memory device.

摘要翻译： 一种在用于半导体存储器件的列冗余集成电路中编程冗余寄存器的方法，其具有被分组在一起的存储器元件列，以形成存储器元件的二维阵列的部分。 列冗余电路包括多个非易失性存储器寄存器，其中每个寄存器与冗余存储器元件的相应冗余列相关联，并且每个寄存器可编程以存储缺陷列的地址和识别代码 缺陷列所属的二维阵列。 当被编程时，每个非易失性存储器寄存器被提供有列地址信号和行地址信号的第一子集。 列地址信号携带有缺陷列的地址，并且行地址信号的第一子集携带识别码。 行地址信号的第二子集的一个信号用于选择多个寄存器中的一个非易失性存储器寄存器，使得由列地址信号和列地址信号所携带的识别码和列的第一子集 地址信号被编程到所选的非易失性存储器寄存器中。 使用现有的列和行地址线来编程冗余存储器寄存器减少了生成专用片上信号的需要，从而最小化存储器件的尺寸。

公开(公告)号：USRE35121E

公开(公告)日：1995-12-12

申请号：US897443

申请日：1992-06-09

申请人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

发明人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC分类号： H01L27/04 ,  G11C5/14 ,  G11C16/30 ,  H01L21/822 ,  H02M3/07 ,  H02M7/25

CPC分类号： G11C5/145 ,  G11C16/30 ,  H02M3/073

摘要： The regulation of the output voltage of a voltage multiplier driven by a ring oscillator, an inverter of which is substituted by a NOR gate for providing a terminal through which stopping the oscillation, is effected by controlling the oscillation frequency in function of the current delivered by the voltage multiplier by means of a transistor T1 working as a current generator connected in series with a regulating chain of series-connected diodes by biasing the gate of the transistor with a constant voltage Vref, thus imposing a reference current Iref through the transistor. The voltage signal across the transistor is fed to the input of a first inverter with a preset triggering threshold and the output signal of the inverter is fed through an amplifying and phase-regenerating stage to said terminal for stopping the oscillation of said NOR gate of the ring oscillator. When the discharge current through the regulating chain becomes greater than the imposed current Iref, across the transistor T1 a voltage signal develops which, beyond a certain threshold, determines the switching of the inverter and, through the amplifying and phase-regenerating stage, causes a stop of the oscillation which resumes only when conduction through the regulating chain stops. At steady state the oscillation frequency will result controlled so as to maintain constant the output voltage of the voltage multiplier and to limit the discharge current through the regulating chain thus limiting power consumption.

摘要翻译： 由环形振荡器驱动的电压倍增器的输出电压的调节通过控制振荡频率来实现，所述环形振荡器的逆变器由NOR门用于提供停止振荡的端子， 通过用作电流发生器的晶体管T1的电压倍增器，其通过以恒定电压Vref偏置晶体管的栅极而与串联二极管的调节链串联连接，从而通过晶体管施加参考电流Iref。 晶体管两端的电压信号以预设的触发阈值馈送到第一反相器的输入端，并且反相器的输出信号通过放大和相位再生级馈送到所述端子，以停止所述NOR门的振荡 环形振荡器。 当通过调节链的放电电流变得大于施加的电流Iref时，跨越晶体管T1产生电压信号，超过一定的阈值，确定逆变器的开关，并且通过放大和相位再生阶段， 仅当通过调节链的导通停止时才恢复振荡的停止。 在稳定状态下，振荡频率将受到控制，以保持电压倍增器的输出电压恒定，并限制放电电流通过调节链，从而限制功耗。

公开(公告)号：US5276644A

公开(公告)日：1994-01-04

申请号：US791453

申请日：1991-11-13

申请人： Luigi Pascucci ,  Marco Olivo

发明人： Luigi Pascucci ,  Marco Olivo

IPC分类号： G11C17/00 ,  G11C7/14 ,  G11C16/06 ,  G11C16/28 ,  G11C7/00

CPC分类号： G11C7/14 ,  G11C16/28

摘要： A non-volatile memory in which, during read operations, the sense amplifier's first input is connected not only to a selected non-programmed reference cell, but also to a current of a value one half the current that flows in a programmed cell; and the sense amplifier's second input is connected not only to a selected matrix cell to be read, but also to a current of a value one half the current that flows in a non-programmed cell.

摘要翻译： 一种非易失性存储器，其中在读取操作期间，读出放大器的第一输入不仅连接到所选择的非编程参考单元，而且还连接到在编程单元中流动的电流的一半的电流; 并且读出放大器的第二输入不仅连接到要读取的所选择的矩阵单元，而且还连接到在非编程单元中流动的电流的一半的电流。

公开(公告)号：US4956569A

公开(公告)日：1990-09-11

申请号：US373203

申请日：1989-06-30

申请人： Marco Olivo ,  Luigi Pascucci ,  Carlo Riva ,  Paolo Rosini ,  Corrado Villa

发明人： Marco Olivo ,  Luigi Pascucci ,  Carlo Riva ,  Paolo Rosini ,  Corrado Villa

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H03K3/356 ,  H03K3/3565 ,  H03K19/003

CPC分类号： H03K19/00315 ,  H03K3/356104 ,  H03K3/3565

摘要： A CMOS logic circuit for converting a low voltage logic signal with a range O-VCC into a high voltage logic signal with a range O-VPP, which may be entirely made with enhancement-type transistors, comprises an additional p-channel, decoupling transistor functionally connected in series with the p-channel transistor of the CMOS circuit which is connected to the high voltage node VPP and the additional decoupling transistor is driven by a bias voltage tied to the VPP voltage and lower than the latter by a certain preset value. The so-called gated breakdown of p-channel transistors is effectively prevented and furthermore these circuits, destined to operate under a high supply voltage, may be fabricated through a normal CMOS fabrication process not requiring particular fabrication techniques for the p-channel transistors subject to gated breakdown conditions or the formation of depletion-type transistors and without the use of special circuits which require oscillator generated driving signals.

公开(公告)号：US4922402A

公开(公告)日：1990-05-01

申请号：US372493

申请日：1989-06-28

申请人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

发明人： Marco Olivo ,  Luigi Pascucci ,  Corrado Villa

IPC分类号： G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC分类号： G11C16/30 ,  G11C5/145 ,  H02M3/073

摘要： A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

公开(公告)号：US5687135A

公开(公告)日：1997-11-11

申请号：US700126

申请日：1996-08-20

申请人： Marco Olivo ,  Marco Maccarrone

发明人： Marco Olivo ,  Marco Maccarrone

IPC分类号： G11C8/04 ,  G11C16/06 ,  H03K21/00 ,  G11C8/00

CPC分类号： H03K21/00 ,  G11C16/06 ,  G11C8/04

摘要： A count unit for performing a number of count operations and wherein, instead of a counter for each count function, provision is made for one counter and a number of registers equal in number to the count functions involved. The registers store the preceding count value and, when their content is to be incremented or in any way altered, load it into the counter which provides for performing the required operation, at the end of which, the content of the counter is stored in the respective register. One of the registers presents a second parallel input for externally loading an initial data which may be transferred to the other registers via the counter.

摘要翻译： 用于执行多个计数操作的计数单元，并且其中，代替每个计数功能的计数器，提供一个计数器和与所涉及的计数功能相等数量的寄存器数量。 寄存器存储上述计数值，当其内容要增加或以任何方式更改时，将其加载到计数器中，该计数器用于执行所需的操作，最后计数器的内容存储在 各自的登记册。 其中一个寄存器提供第二个并行输入，用于外部加载初始数据，初始数据可以通过计数器传输到其他寄存器。