公开(公告)号：US20240242757A1

公开(公告)日：2024-07-18

申请号：US18297055

申请日：2023-04-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Feng-Min LEE ,  Po-Hao TSENG ,  Yu-Yu LIN ,  Ming-Hsiu LEE

IPC: G11C11/4096 ,  G11C11/405

CPC classification number: G11C11/4096 ,  G11C11/405

Abstract: A universal memory for In-Memory Computing and an operation method thereof are provided. The universal memory includes at least one write word line, at least one unit cell and at least one read word line. The unit cell includes a write transistor and a read transistor. The gate of the write transistor is connected to the write word line. The write transistor is a transistor with adjustable threshold voltage. The gate of the read transistor is connected to the drain or the source of the write transistor. The read word line is connected to the drain or the source of the read transistor. The universal memory is used for a training mode and an inference mode. In the training mode and the inference mode, a weight is stored at different locations of the unit cell.

公开(公告)号：US20240161826A1

公开(公告)日：2024-05-16

申请号：US18420874

申请日：2024-01-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Ming-Hsiu LEE

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/046 ,  G11C16/0475 ,  G11C2211/4016

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. The current sensing units are coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units. Each memory cell includes a first transistor, a second transistor and an inverter. The first search line is coupled to the second search line by the inverter.

公开(公告)号：US20230282292A1

公开(公告)日：2023-09-07

申请号：US17686469

申请日：2022-03-04

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

Abstract: A memory device, which includes a first driving circuit, a second driving circuit, a sensing circuit and an in-memory search (IMS) array. Memory units of the in-memory search array are arranged as a plurality of horizontal rows and vertical columns. Control terminal of each the memory unit in the same vertical column is coupled to the first driving circuit through a word line. The memory units of the same vertical column are connected in series and coupled to the second driving circuit through a bit line, and coupled to the sensing circuit through a source line. Every 2N adjacent memory units in the same vertical column are arranged as a memory unit to store an encoded data of 2N bits corresponding to an original data of M bits, where N and M are positive integers, and N is greater than or equal to two.

公开(公告)号：US20230238061A1

公开(公告)日：2023-07-27

申请号：US17717192

申请日：2022-04-11

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hsuan LIN ,  Po-Hao TSENG

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: The application provides a content addressable memory (CAM) memory device, a CAM memory cell and a method for searching and comparing data thereof. The CAM memory device includes: a plurality of CAM memory cells; and an electrical characteristic detection circuit coupled to the CAM memory cells; wherein in data searching, a search data is compared with a storage data stored in the CAM memory cells, the CAM memory cells generate a plurality of memory cell currents, the electrical characteristic detection circuit detects the memory cell currents to generate a plurality of sensing results, or the electrical characteristic detection circuit detects a plurality of match line voltages on a plurality of match lines coupled to the CAM memory cells to generate the plurality of search results; and the storage data is a single-bit multi-level storage data and/or the search data is a single-bit multi-level search data.

公开(公告)号：US20220068386A1

公开(公告)日：2022-03-03

申请号：US17333046

申请日：2021-05-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Feng-Min LEE ,  Ming-Hsiu LEE ,  Liang-Yu CHEN ,  Yun-Yuan WANG

IPC: G11C15/04

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

公开(公告)号：US20250087268A1

公开(公告)日：2025-03-13

申请号：US18367075

申请日：2023-09-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/10

Abstract: A non-volatile 3D memory search architecture provides for receiving searches for application to select lines and word lines of a non-volatile 3D memory array. The architecture uses two word lines per unit of information of the searches and two memory devices per unit of stored feature to search against. The architecture uses respective bit lines of the non-volatile 3D memory array as respective matching lines for searching. Respective memory strings (e.g., NAND memory strings) of the non-volatile 3D memory array are usable to store respective data values, e.g., corresponding to elements to search for. Respective pluralities of the memory strings are coupled in parallel to respective shared bit lines. The architecture has applicability to comparing and sorting, in addition to searching in application areas such as artificial intelligence (AI) and big data.

公开(公告)号：US20240370228A1

公开(公告)日：2024-11-07

申请号：US18143777

申请日：2023-05-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG

IPC: G06F7/544 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26

Abstract: A system based on computational memory and memory systems, such as embodied in computational solid state drive (SSD) technology, as described herein, reduces processor utilization and/or bus bandwidth utilization. The system is enabled to perform computational techniques (e.g., searching, computing, and/or accessing) using resources of the computational SSDs, rather than processor and/or bus resources, thus reducing or minimizing information movement between processing elements and storage devices. Computational SSD technology enables managing, organizing, selecting, and analyzing ever increasing data volume in real time. A computational SSD is enabled to store and to operate on data locally, e.g., using resources of the computational SSD. Thus, processing, storage, and bandwidth requirements of a system are reduced by using the computational SSD.

公开(公告)号：US20240339162A1

公开(公告)日：2024-10-10

申请号：US18744776

申请日：2024-06-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/08 ,  G11C16/102 ,  G11C16/26 ,  G11C16/30

Abstract: An encoding method is provided for a memory device which includes an in-memory search (IMS) array having several memory units. The memory units in a same horizontal row are coupled to a first driving circuit through corresponding word lines and coupled to a sensing circuit through a match signal line. Every 2N adjacent memory units in the same horizontal row are arranged as a memory cell. An original data of M-bits is encoded to an encoded data of 2N-bits with a first encoded area including the first to N-th bits of the encoded data and a second encoded area including the (N+1)-th to 2N-th bits of the encoded data. The M bits of the original data have an equivalent binary value increased by an incremental step which is P times of an incremental step for the N bits of the first encoded area.

公开(公告)号：US20240194229A1

公开(公告)日：2024-06-13

申请号：US18064303

申请日：2022-12-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yun-Yuan WANG ,  Cheng-Hsien LU ,  Po-Hao TSENG ,  Ming-Hsiu LEE

IPC: G11C7/10 ,  G11C7/14 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G11C7/14 ,  G11C8/08

Abstract: The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.

公开(公告)号：US20240021254A1

公开(公告)日：2024-01-18

申请号：US17812243

申请日：2022-07-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Hao TSENG ,  Tian-Cih BO

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/3404 ,  G11C16/30 ,  G11C16/26

Abstract: A memory device for in-memory search is provided. The memory device includes a plurality of memory cells, and each of the memory cells stores a stored data and receives a search data, including a first transistor and a second transistor. The first transistor has a first threshold voltage and receives a first gate bias. The second transistor is connected to the first transistor, and the second transistor has a second threshold voltage and receives a second gate bias. The stored data is encoded according to the first threshold voltage and the second threshold voltage, and the search data is encoded according to the first gate bias and the second gate bias. There is a mismatch distance between the stored data and the search data. An output current generated by each of the memory cells is related to the mismatch distance.