公开(公告)号：US10255073B2

公开(公告)日：2019-04-09

申请号：US15592551

申请日：2017-05-11

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Sean Steedman ,  Brent Loertscher

IPC: G06F9/30 ,  G06F1/08 ,  G06F13/40 ,  G06F9/34

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

公开(公告)号：US09467141B2

公开(公告)日：2016-10-11

申请号：US13633429

申请日：2012-10-02

Applicant: Microchip Technology Incorporated

Inventor： Zeke Lundstrum ,  Keith Curtis ,  Burke Davison ,  Sean Steedman ,  Yann LeFaou

IPC: H03K17/96

CPC classification number: H03K17/962 ,  H03K17/9622 ,  H03K2217/960705 ,  H03K2217/960765

Abstract: A microcontroller measures capacitance of capacitive sensors having guard rings associated therewith. A guard ring is provided around each capacitive sensor plate and is charged to substantially the same voltage as a voltage on the associated capacitive sensor plate. The guard ring reduces parasitic capacitances of the capacitive sensor plate caused by differences in voltage potentials between the capacitive sensor plate, and adjacent circuit conductors, ground planes and power planes. An analog output is buffered and coupled to an analog input coupled to the capacitive sensor plate, and is used to drive the guard ring voltage to substantially the same voltage as the voltage on the capacitive sensor plate.

Abstract translation: 微控制器测量具有与其相关联的保护环的电容传感器的电容。 在每个电容传感器板周围设置保护环，并将其与相关联的电容式传感器板上的电压基本相同的电压充电。 保护环降低由电容式传感器板和相邻的电路导体，接地层和电源平面之间的电位差的差异引起的电容传感器板的寄生电容。 模拟输出被缓冲并耦合到耦合到电容传感器板的模拟输入，并用于将保护环电压驱动到与电容传感器板上的电压基本相同的电压。

公开(公告)号：US20140253212A1

公开(公告)日：2014-09-11

申请号：US14199838

申请日：2014-03-06

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Sean Steedman ,  Fanie Duvenhage

IPC: H03K3/356

CPC classification number: H03K3/356104 ,  G06F1/3243 ,  H03K19/018557 ,  H03K19/018585 ,  Y02D10/152

Abstract: An integrated circuit including a processor configured to operate off a supply voltage being applied at one of a plurality of external pins; and internal input/output circuitry configured to select between the supply voltage and at least one other supply voltage being applied at another of the plurality of external pins.

Abstract translation: 一种集成电路，包括：处理器，被配置为操作断开施加在多个外部引脚中的一个上的电源电压; 以及内部输入/输出电路，其被配置为在所述电源电压和在所述多个外部引脚中的另一个上施加的至少一个其它电源电压之间进行选择。

公开(公告)号：US20130254476A1

公开(公告)日：2013-09-26

申请号：US13830377

申请日：2013-03-14

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： Zeke Lundstrum ,  Fanie Duvenhage ,  Sean Steedman ,  Kevin Lee Kilzer ,  Joseph Julicher

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract translation: 微处理器或微控制器设备可以具有中央处理单元（CPU），与CPU耦合的数据存储器，其中数据存储器被分成多个存储体，其中存储体选择寄存器确定当前与 中央处理器。 此外，提供第一和第二组特殊功能寄存器，其中在上下文切换发生时，第一组或第二组特殊功能寄存器被选择为用于CPU和相应的另一组特殊功能寄存器的活动上下文寄存器 被选择为非活动上下文寄存器，其中活动上下文寄存器的至少一些寄存器被存储器映射到数据存储器的多于两个存储体，并且其中非活动上下文寄存器的所有寄存器被存储器映射到至少一个存储器位置 在数据存储器内。

公开(公告)号：US20130088372A1

公开(公告)日：2013-04-11

申请号：US13633523

申请日：2012-10-02

Applicant: Microchip Technology Incorporated

Inventor： Zeke Lundstrum ,  Keith Curtis ,  Burke Davison ,  Sean Steedman ,  Yann LeFaou

IPC: H03K17/955 ,  H03M1/00 ,  H03M1/12

CPC classification number: H03K17/9622 ,  H03K2217/960725 ,  H03K2217/960765 ,  H03K2217/96077

Abstract: A guard ring is provided around each capacitive sensor plate and charged to substantially the same voltage as a voltage on the capacitive sensor plate. The guard ring reduces parasitic capacitances of the capacitive sensor plate caused by differences in voltage potentials between the capacitive sensor plate, and adjacent circuit conductors, ground planes and power planes. Two digital outputs and associated voltage divider resistors are used to drive the guard ring voltage to substantially the same voltage as the voltage on the capacitive sensor plate.

Abstract translation: 在每个电容传感器板周围设置保护环，并将其充电到与电容式传感器板上的电压基本相同的电压。 保护环降低由电容式传感器板和相邻的电路导体，接地层和电源平面之间的电位差的差异引起的电容传感器板的寄生电容。 两个数字输出和相关的分压电阻用于将保护环电压驱动到与电容传感器板上的电压基本相同的电压。

公开(公告)号：US10114776B2

公开(公告)日：2018-10-30

申请号：US15498846

申请日：2017-04-27

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman ,  Kevin Kilzer ,  Ashish Senapati ,  Justin Milks ,  Prashanth Pulipaka

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/362 ,  G06F13/26 ,  G06F13/28 ,  G06F13/40 ,  G06F13/34

Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.

公开(公告)号：US20170329611A1

公开(公告)日：2017-11-16

申请号：US15592551

申请日：2017-05-11

Applicant: Microchip Technology Incorporated

Inventor： Ashish Senapati ,  Sean Steedman ,  Brent Loertscher

IPC: G06F9/30 ,  G06F13/40 ,  G06F1/08

CPC classification number: G06F9/30149 ,  G06F1/08 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30178 ,  G06F9/30185 ,  G06F9/342 ,  G06F13/4018

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16 KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4 KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

公开(公告)号：US20170052799A1

公开(公告)日：2017-02-23

申请号：US15241851

申请日：2016-08-19

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman

IPC: G06F9/445 ,  G06F13/40

CPC classification number: G06F9/44505 ,  G06F1/3293 ,  G06F13/4022 ,  G06F15/7807

Abstract: An integrated circuit device includes a first processing core operable to process a first instruction set, a second processing core operable to process a second instruction set different from the first instruction set, a plurality of peripheral devices, a memory and a switching circuit configured to couple the memory and the plurality of peripheral devices with either the first processing core or the second processing core depending on a configuration setting of the integrated circuit device.

Abstract translation: 集成电路装置包括可操作以处理第一指令集的第一处理核心，可操作以处理与第一指令集不同的第二指令集的第二处理核心，多个外围设备，存储器和切换电路， 存储器和具有第一处理核心或第二处理核心的多个外围设备，这取决于集成电路设备的配置设置。

公开(公告)号：US20160350246A1

公开(公告)日：2016-12-01

申请号：US15169352

申请日：2016-05-31

Applicant: Microchip Technology Incorporated

Inventor： Sean Steedman ,  Yong Yuenyongsgool ,  Jacobus Albertus van Eeden ,  David Otten ,  Naveen Raj ,  Prashanth Pulipaka ,  Prasanna Surakanti

IPC: G06F13/30 ,  G06F13/37

CPC classification number: G06F13/30 ,  G06F13/28 ,  G06F13/37

Abstract: An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.

Abstract translation: 公开了一种嵌入式系统及其控制方法。 嵌入式系统包括包括多个通道的直接存储器控制器，其中多个通道仲裁方案是可编程的，其中DMA控制器是可编程的，以将特定通道上的块数据传输分割为多个单独的数据传输，其中a 指定通道上的数据传输可以在数据传输的单独数据传输之间中断。

公开(公告)号：US09195497B2

公开(公告)日：2015-11-24

申请号：US13830377

申请日：2013-03-14

Applicant: Microchip Technology Incorporated

Inventor： Zeke Lundstrum ,  Fanie Duvenhage ,  Sean Steedman ,  Kevin Lee Kilzer ,  Joseph Julicher

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4812 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract translation: 微处理器或微控制器设备可以具有中央处理单元（CPU），与CPU耦合的数据存储器，其中数据存储器被分成多个存储体，其中存储体选择寄存器确定当前与 中央处理器。 此外，提供第一和第二组特殊功能寄存器，其中在上下文切换发生时，第一组或第二组特殊功能寄存器被选择为用于CPU和相应的另一组特殊功能寄存器的活动上下文寄存器 被选择为非活动上下文寄存器，其中活动上下文寄存器的至少一些寄存器被存储器映射到数据存储器的多于两个存储体，并且其中非活动上下文寄存器的所有寄存器被存储器映射到至少一个存储器位置 在数据存储器内。