公开(公告)号：US20230317172A1

公开(公告)日：2023-10-05

申请号：US18205679

申请日：2023-06-05

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/14 ,  H10B41/27 ,  H10B41/35 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H10B41/27 ,  H10B41/35

Abstract: Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US11694763B2

公开(公告)日：2023-07-04

申请号：US17700085

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G06F11/30 ,  G06F11/07 ,  G11C29/12

CPC classification number: G11C29/44 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037 ,  G11C29/12005 ,  G11C29/42

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US20230148018A1

公开(公告)日：2023-05-11

申请号：US18095646

申请日：2023-01-11

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Sundararajan Sankaranarayanan ,  Eric Nien-Heng Lee ,  Akira Goda

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C11/4093 ,  G11C11/4074 ,  G11C16/34 ,  G11C16/26 ,  G11C2211/5642 ,  G11C16/0483

Abstract: A device includes an array of memory cells with a first word line coupled to at least a subset of the array of memory cells and control logic coupled to the first word line. The control logic to detect, within a queue, a first read command to read first data from a first page of the subset and a second read command to read second data from a second page of the subset. The control logic is further to cause a voltage applied to the first word line to move to a target value. The control logic is further to cause a page buffer to sense the first data from a first bit line coupled to the first page and to sense the second data from a second bit line coupled to the second page. The control logic is further to cause the first word line to be discharged.

公开(公告)号：US20220392533A1

公开(公告)日：2022-12-08

申请号：US17888041

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US20220359767A1

公开(公告)日：2022-11-10

申请号：US17814164

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Marc Aoulaiche

IPC: H01L29/786 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L29/10

Abstract: An apparatus comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, a first channel material extending vertically through the stack, and a second channel material adjacent the first channel material and extending vertically through the stack. The first channel material has a first band gap and the second channel material has a second band gap that is relatively larger than the first band gap. The apparatus further comprises a conductive plug structure adjacent to each of the first channel material and the second channel material, and a conductive line structure adjacent to the conductive plug structure. Methods of forming the apparatus, memory devices, and electronic systems are also described.

公开(公告)号：US11481273B2

公开(公告)日：2022-10-25

申请号：US16995359

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo′ Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06 ,  G06F11/10

Abstract: A memory component comprises a cyclic buffer partition portion and a snapshot partition portion. In response to receiving a signal that a trigger event has occurred, a processing device included in the memory component performs an error correction operation on a portion of data stored in the cyclic buffer partition portion, copies the data stored in the cyclic buffer partition portion to the snapshot partition portion in response to the error correction operation being successful, and sends the data stored in the cyclic buffer partition portion to a processing device operatively coupled to the memory component in response to the error correction operation not being successful.

公开(公告)号：US20220291865A1

公开(公告)日：2022-09-15

申请号：US17829861

申请日：2022-06-01

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06 ,  G06F1/26

Abstract: A system includes a processing device and a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion and a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can further include a first sub-partition portion having a first programming characteristic and a second sub-partition portion having a second programming characteristic. The processing device can write received data sequentially to the cycle buffer partition portion and write, based at least in part on a determination that a trigger event has occurred, data from the cyclic buffer partition portion to the first sub-partition portion or the second sub-partition portion, or both.

公开(公告)号：US20220215895A1

公开(公告)日：2022-07-07

申请号：US17700085

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G06F11/30 ,  G06F11/07 ,  G11C29/12

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.

公开(公告)号：US11288160B2

公开(公告)日：2022-03-29

申请号：US16995246

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, Jr. ,  Niccolo′ Righetti ,  Kishore K. Muchherla ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/30 ,  G11C5/14 ,  G11C16/34

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

公开(公告)号：US20220057944A1

公开(公告)日：2022-02-24

申请号：US17001121

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Kishore K. Muchherla ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device is further coupled to the processing device and to a primary power supply and a secondary power supply. The processing device is to determine, based at least in part on availability of the primary power supply to the memory device, whether to operate the memory device with a first trim tailored to data reliability or a second trim tailored to programming time. The processing device is further to operate the memory device with the determined one of the first trim or the second trim.