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公开(公告)号：US20140043912A1
公开(公告)日：2014-02-13
申请号：US14045492
申请日：2013-10-03
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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公开(公告)号：US20220115071A1
公开(公告)日：2022-04-14
申请号：US17555728
申请日：2021-12-20
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to program each memory cell of a plurality of memory cells whose respective data state is higher than or equal to a first particular data state of a plurality of data states while inhibiting programming of each memory cell of the plurality of memory cells whose respective data state is lower than the first particular data state, and program each memory cell of the plurality of memory cells whose respective data state is lower than or equal to a second particular data state of the plurality of data states after programming each memory cell of the plurality of memory cells whose respective data state is higher than or equal to the first particular data state.
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Patent Agency Ranking
公开(公告)号：US11004513B2
公开(公告)日：2021-05-11
申请号：US16752981
申请日：2020-01-27
Applicant: Micron Technology, Inc.
Inventor： Allahyar Vahidimowlavi , Kalyan C. Kavalipurapu
Abstract: Memory devices with controlled wordline ramp rates and associated systems and methods are disclosed herein. In one embodiment, a memory device includes at least one voltage regulator and a plurality of wordlines. The memory device is configured, during a programming operation of the memory region, to ramp a selected wordline to a desired programming voltage while ramping one or more adjacent, unselected wordlines electrically coupled to the selected wordline to desired inhibit voltage(s) using the at least one voltage regulator. In some embodiments, the memory device ramps the selected wordline and the one or more adjacent, unselected wordlines such that the one or more adjacent, unselected wordlines reach the desired inhibit voltage(s) when the selected wordline reaches the desired programming voltage. In these and other embodiments, the memory device ramps the selected wordline to the desired programming voltage without floating the selected wordline.
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公开(公告)号：US10770145B2
公开(公告)日：2020-09-08
申请号：US16298313
申请日：2019-03-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
Abstract: Method of operating a memory include increasing respective threshold voltages of a first subset of memory cells of a plurality of memory cells to threshold voltage levels higher than a particular voltage level in response to applying a first plurality of programming pulses, and subsequently increasing respective threshold voltages of a second subset of memory cells of the plurality of memory cells to threshold voltage levels lower than the particular voltage level in response to applying a second plurality of programming pulses, wherein the first plurality of programming pulses have respective voltage levels within a first range of voltage levels, the second plurality of programming pulses have respective voltage levels within a second range of voltage levels, and a lowest voltage level of the first range of voltage levels is lower than or equal to a highest voltage level of the second range of voltage levels.
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公开(公告)号：US20180096722A1
公开(公告)日：2018-04-05
申请号：US15831718
申请日：2017-12-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
CPC classification number: G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
Abstract: Memory devices include control logic configured to set a first start program voltage and a first stop program voltage, to load actual first data for cells to be programmed to a level greater than or equal to a first level, and to load inhibit data for cells to be programmed to a level less than a second level. After programming the cells to be programmed to the level greater than or equal to the first level, the control logic is further configured to set a second start program voltage and a second stop program voltage, to load inhibit data for the cells programmed to the level greater than or equal to the first level, and to load actual second data for the cells to be programmed to the level less than the second level, wherein the first level is one level higher than the second level.
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公开(公告)号：US09502101B2
公开(公告)日：2016-11-22
申请号：US14725749
申请日：2015-05-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Vishal Sarin , Allahyar Vahidimowlavi
CPC classification number: G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
Abstract: A first memory cell is programmed to a first level using a first set of program pulses within a first programming voltage range. A second memory cell to be programmed to a second level less than the first level is inhibited while programming the first memory cell to the first level. After programming the first memory cell to the first level, the second memory cell is programmed to the second level using a second set of program pulses within a second programming voltage range, where the first programming voltage range overlaps the second programming voltage range. The first memory cell that is programmed to the first level is inhibited while programming the second memory cell to the second level.
Abstract translation: 使用第一编程电压范围内的第一组编程脉冲将第一存储单元编程为第一电平。 在将第一存储器单元编程到第一电平时，禁止要编程到小于第一电平的第二电平的第二存储器单元。 在将第一存储器单元编程到第一电平之后，使用第二编程电压范围内的第二组编程脉冲将第二存储单元编程为第二电平，其中第一编程电压范围与第二编程电压范围重叠。 在将第二存储器单元编程到第二级时，禁止编程到第一级的第一存储单元。
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公开(公告)号：US09025388B2
公开(公告)日：2015-05-05
申请号：US14045492
申请日：2013-10-03
Applicant: Micron Technology, Inc.
Inventor： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC: G11C16/04 , G11C16/10 , G11C11/56 , G11C16/34 , G11C11/404
CPC classification number: G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。
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