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公开(公告)号：US12002510B2
公开(公告)日：2024-06-04
申请号：US17588718
申请日：2022-01-31
Applicant: Micron Technology, Inc.
Inventor： Andrea Ghetti , Andrea Martinelli , Efrem Bolandrina , Ferdinando Bedeschi , Paolo Fantini
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0004 , G11C2213/15 , G11C2213/30
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.
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公开(公告)号：US08988926B2
公开(公告)日：2015-03-24
申请号：US13739387
申请日：2013-01-11
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
CPC classification number: H01L45/1253 , G11C13/0004 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/124 , H01L45/144 , H01L45/16 , H01L45/1691
Abstract: Embodiments disclosed herein may relate to forming a storage component comprising a phase change material and a shunt relative to amorphous portions of the phase change material.
Abstract translation: 本文公开的实施例可涉及形成相对于相变材料的非晶部分包括相变材料和分路的存储部件。
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公开(公告)号：US20140198565A1
公开(公告)日：2014-07-17
申请号：US13739387
申请日：2013-01-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
CPC classification number: H01L45/1253 , G11C13/0004 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/12 , H01L45/124 , H01L45/144 , H01L45/16 , H01L45/1691
Abstract: Embodiments disclosed herein may relate to forming a storage component comprising a phase change material and a shunt relative to amorphous portions of the phase change material.
Abstract translation: 本文公开的实施例可涉及形成相对于相变材料的非晶部分包括相变材料和分路的存储部件。
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Patent Agency Ranking
公开(公告)号：US20230245701A1
公开(公告)日：2023-08-03
申请号：US17588718
申请日：2022-01-31
Applicant: Micron Technology, Inc.
Inventor： Andrea Ghetti , Andrea Martinelli , Efrem Bolandrina , Ferdinando Bedeschi , Paolo Fantini
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0028 , G11C13/0026 , G11C13/004 , G11C13/003 , G11C13/0004 , G11C2213/30 , G11C2213/15
Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a vertical three-dimensional cross-point memory device uses digit line decoders that include, on the digit line side of memory cells, a current limiter and sensing circuit configured to control program current in either of positive or negative program polarities, as selected by a controller. Two current limiters are each used on the digit line side of each memory cell. A negative polarity current limiter is used for pull-up, and a positive polarity current limiter is used for pull-down. A negative polarity sensing circuit is used between the respective digit line decoder and a positive supply voltage. A positive polarity sensing circuit is used between the respective digit line decoder and a negative supply voltage. The current limiter and sensing circuit pair of the same polarity is coupled to each digit line decoder based on the selected program polarity.
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公开(公告)号：US11114613B2
公开(公告)日：2021-09-07
申请号：US16866302
申请日：2020-05-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US20190288194A1
公开(公告)日：2019-09-19
申请号：US16360756
申请日：2019-03-21
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US20180006217A1
公开(公告)日：2018-01-04
申请号：US15689256
申请日：2017-08-29
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
CPC classification number: H01L45/06 , H01L27/2427 , H01L27/2463 , H01L27/249 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
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公开(公告)号：US20160056208A1
公开(公告)日：2016-02-25
申请号：US14468036
申请日：2014-08-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Andrea Ghetti
CPC classification number: H01L45/06 , H01L27/2427 , H01L27/2463 , H01L27/249 , H01L45/1233 , H01L45/144 , H01L45/1675
Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.
Abstract translation: 所公开的技术通常涉及集成电路器件，特别涉及交叉点存储器阵列及其制造方法。 形成线堆叠，包括设置在导线下方的存储材料线。 上导电线形成在线堆叠上并与线堆叠交叉，使相邻的上导线之间的线堆叠的部分暴露。 在形成上导线之后，通过从线堆叠的暴露部分去除存储材料，使得每个存储元件被空间横向包围，在下导电线和上导线之间的交叉处形成存储元件。 连续的密封材料横向围绕每个存储元件。
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