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    Discharge current mitigation in a memory array
    3.
    发明授权
    Discharge current mitigation in a memory array 有权

    公开(公告)号：US11417375B2

    公开(公告)日：2022-08-16

    申请号：US17085154

    申请日：2020-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Hongmei Wang ,  Jin Seung Son ,  Andrea Ghetti

    IPC: G11C8/08 ,  G11C7/12

    Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

    Cross-point memory and methods for forming of the same
    4.
    发明授权
    Cross-point memory and methods for forming of the same 有权

    公开(公告)号：US10680170B2

    公开(公告)日：2020-06-09

    申请号：US16360756

    申请日：2019-03-21

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

    IPC: H01L29/06 ,  H01L45/00 ,  H01L27/24

    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

    ASYMMETRIC VERTICAL THIN FILM TRANSISTOR SELECTOR
    6.
    发明申请
    ASYMMETRIC VERTICAL THIN FILM TRANSISTOR SELECTOR 有权

    公开(公告)号：US20250040182A1

    公开(公告)日：2025-01-30

    申请号：US18781766

    申请日：2024-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Andrea Ghetti ,  Benjamin Chu-Kung ,  Sara Moon Villa

    IPC: H01L29/786 ,  G11C16/04 ,  H01L29/417 ,  H01L29/66 ,  H10B41/27

    Abstract: Systems, methods, and apparatuses are provided for an asymmetric vertical thin film transistor selector. An apparatus includes first and second source/drain regions formed on a substrate, a channel separating the first source/drain region and the second source/drain region, and a gate separated from the channel by a gate dielectric material. The first source/drain region, the second source/drain region, the channel, and the gate form a vertical thin film transistor, a first end of the channel is coupled to the first source/drain region and extends beyond a first end of the gate, and a second end of the channel is coupled to the second source/drain region and does not extend beyond a second end of the gate that is opposite the first end of the gate. A contact in the substrate is coupled to the first source/drain region and a sense line is coupled to the second source/drain region.

    DISCHARGE CURRENT MITIGATION IN A MEMORY ARRAY
    7.
    发明申请
    DISCHARGE CURRENT MITIGATION IN A MEMORY ARRAY 有权

    公开(公告)号：US20210183421A1

    公开(公告)日：2021-06-17

    申请号：US17085154

    申请日：2020-10-30

    Applicant: Micron Technology, Inc.

    Inventor： Hongmei Wang ,  Jin Seung Son ,  Andrea Ghetti

    IPC: G11C8/08 ,  G11C7/12

    Abstract: Methods, systems, and devices for discharge current mitigation in a memory array are described. Access lines of a memory array may be divided into discrete segments, with each segment coupled with a driver for the access line by one or more vias respective to the segment. For example, a first segment of an access line may be coupled with a first set of memory cells, a second segment of the access line may be coupled with a second set of memory cells, and a driver may be coupled to the first segment by a first via and to the second segment by a second via. To access a memory cell in either the first set or the second, both the first segment of the access line and the second segment of the access line may be activated together by the common driver.

    CROSS-POINT MEMORY AND METHODS FOR FORMING OF THE SAME
    8.
    发明申请
    CROSS-POINT MEMORY AND METHODS FOR FORMING OF THE SAME 审中-公开

    公开(公告)号：US20200266343A1

    公开(公告)日：2020-08-20

    申请号：US16866302

    申请日：2020-05-04

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

    Cross-point memory and methods for forming of the same
    9.
    发明授权
    Cross-point memory and methods for forming of the same 有权

    公开(公告)号：US10283703B2

    公开(公告)日：2019-05-07

    申请号：US15689256

    申请日：2017-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Andrea Ghetti

    IPC: H01L45/00 ,  H01L27/24

    Abstract: The disclosed technology generally relates to integrated circuit devices, and in particular to cross-point memory arrays and methods for fabricating the same. Line stacks are formed, including a storage material line disposed over lower a conductive line. Upper conductive lines are formed over and crossing the line stacks, exposing portions of the line stacks between adjacent upper conductive lines. After forming the upper conductive lines, storage elements are formed at intersections between the lower conductive lines and the upper conductive lines by removing storage materials from exposed portions of the line stacks, such that each storage element is laterally surrounded by spaces. A continuous sealing material laterally surrounds each of the storage elements.

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