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公开(公告)号：US11710534B1
公开(公告)日：2023-07-25
申请号：US17682837
申请日：2022-02-28
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , Scott E. Smith , Manoj Vijay
CPC classification number: G11C29/52 , G11C29/021 , G11C29/12005 , G11C29/38 , G11C29/46 , G11C29/787 , G11C2029/0409
Abstract: Embodiments presented herein are directed to testing and/or debugging a memory device of a memory module (e.g., a dual in-line memory module (DIMM)) without having to remove the DIMM from a corresponding computing device and without having to interrupt operation of the computing device. A particular memory device (e.g., DRAM) may be identified for testing and/or debugging based on a failure message. However, the failure message may not identify a specific location or hardware of the module that caused the failure. Embodiments presented herein provide techniques to obtain data for analysis to determine and/or deliver a cause of the failure while reducing or eliminating downtime of the computing device. Test modes to do so may include a synchronous test mode, an asynchronous test mode, and an analog compare mode. A test mode may be selected based on the failure or a signal/function of the DRAM to be tested or debugged.
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12.发明申请公开(公告)号：US20230037349A1
公开(公告)日：2023-02-09
申请号：US17965561
申请日：2022-10-13
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , Scott E. Smith
IPC: H01L25/065 , G01R27/14 , H01L23/538
Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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公开(公告)号：US11437116B2
公开(公告)日：2022-09-06
申请号：US16852239
申请日：2020-04-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christian N. Mohr , Gregg D. Wolff , Christopher G. Wieduwilt , C. Omar Benitez , Dennis G. Montierth
Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
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Patent Agency Ranking
公开(公告)号：US10714156B2
公开(公告)日：2020-07-14
申请号：US16121325
申请日：2018-09-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christian N. Mohr , Jennifer E. Taylor , Vijayakrishna J. Vankayala
Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
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公开(公告)号：US20200075067A1
公开(公告)日：2020-03-05
申请号：US16121325
申请日：2018-09-04
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christian N. Mohr , Jennifer E. Taylor , Vijayakrishna J. Vankayala
IPC: G11C7/10
Abstract: Apparatuses and methods for trimming input buffers based on identified mismatches. An example apparatus includes an input buffer having a first input stage circuit configured to receive a first signal, a second input stage circuit configured to receive a second signal, and an output stage coupled to the first and second input stage circuits and configured to provide an output signal. The first input stage circuit includes serially-coupled transistor pairs that are each coupled between the output stage and a bias voltage. Each of the plurality of serially-coupled transistors pairs are selectively enabled in response to a respective enable signal. The apparatus further including a trim circuit coupled to the first input stage circuit and comprising a plurality of programmable components. The trim circuit is configured to be programmed to provide the respective enable signals based on a detected transition voltage offset relative to a target transition voltage.
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公开(公告)号：US20200005885A1
公开(公告)日：2020-01-02
申请号：US16020806
申请日：2018-06-27
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , Gregg D. Wolff , Christopher G. Wieduwilt , C. Omar Benitez , Dennis G. Montierth
Abstract: An apparatus may include a memory array, a test circuit coupled to the memory array, a counter circuit coupled to the test circuit and an input/output (I/O) circuit coupled to the counter circuit. During a test operation, the test circuit may receive blocks of data from the memory array and compare the data to detect errors in the blocks of data. The counter circuit may increment a count value in response to detection of an error by the test circuit, and the I/O circuit may provide the count value to an output. The test circuit may also provide test comparison data based on the received blocks of data, and the I/O circuit may provide one of the count value and the test comparison data to the output.
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公开(公告)号：US10957364B2
公开(公告)日：2021-03-23
申请号：US16143105
申请日：2018-09-26
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , John E. Riley
Abstract: Memory devices may have internal circuitry that employs voltages higher and/or lower than voltages provided by an external power source. Charge pumps are DC/DC converters that may be used to generate the higher voltages internally. The number of available charge pumps in a memory device may be conservatively dimensioned to be high, in some systems to protect yields. Some of the available charge pumps may be disabled during manufacturing or testing to reduce the number of active charge pumps. The testing process may employ dedicated logic in the memory device and the disabling may employ fuse circuitry.
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18.发明授权公开(公告)号：US10692841B2
公开(公告)日：2020-06-23
申请号：US16020140
申请日：2018-06-27
Applicant: Micron Technology, Inc.
Inventor： Christian N. Mohr , Scott E. Smith
IPC: H01L21/66 , G01R31/26 , H01L25/065 , G01R27/14 , H01L23/538
Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.
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