公开(公告)号：US20190362759A1

公开(公告)日：2019-11-28

申请号：US16537775

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata

IPC: G11C7/06 ,  G11C8/12 ,  H03K19/20 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/08

Abstract: The present disclosure includes apparatuses and methods related to selectively performing logical operations. An example apparatus comprises sensing circuitry including a sense amplifier and a compute component. A controller is coupled to sensing circuitry and is configured to cause storing of an indication of whether a logical operation is to be selectively performed between an operand stored in the sensing circuitry and an operand stored in the sense amplifier.

公开(公告)号：US20190341084A1

公开(公告)日：2019-11-07

申请号：US16514371

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Harish N. Venkata ,  Guy S. Perry

IPC: G11C7/06 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/403 ,  G11C7/12 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

Abstract: The present disclosure includes apparatuses and methods related to storing a data value in a sensing circuitry element. An example method comprises sensing a first data value with a sense amplifier of a sensing circuitry element, moving a second data value from a first storage location of a compute component to a second storage location of the compute component, and storing, in the first storage location, a third data value resulting from a logical operation performed on the first data value and the second data value. The logical operation can be performed by logic circuitry of the sensing circuitry element.

公开(公告)号：US20190325937A1

公开(公告)日：2019-10-24

申请号：US16457403

申请日：2019-06-28

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4096 ,  G11C7/10 ,  G11C7/22

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

公开(公告)号：US10452319B1

公开(公告)日：2019-10-22

申请号：US16019116

申请日：2018-06-26

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Liang Chen

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4076

Abstract: A host device and memory device function together to perform internal write leveling of a data strobe with a write command within the memory device. The memory device includes a command interface configured to receive write commands from the host device. The memory device also includes an input-output interface configured to receive the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal based at least in part on the write commands. The launch of the internal write signal is based at least in part on an indication from the host device that indicates when to launch the internal write signal relative to a cas write latency (CWL) for the memory device.

公开(公告)号：US20190244655A1

公开(公告)日：2019-08-08

申请号：US15891356

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4096 ,  G06F13/16 ,  G11C7/22 ,  G11C7/10 ,  G06F13/40 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G06F13/1689 ,  G06F13/4063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4094

Abstract: Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

公开(公告)号：US10366742B1

公开(公告)日：2019-07-30

申请号：US15891356

申请日：2018-02-07

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G06F13/16 ,  G11C11/4096 ,  G11C7/22 ,  G11C7/10 ,  G11C11/4094 ,  G06F13/40

CPC classification number: G11C11/4096 ,  G06F13/1689 ,  G06F13/4063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4094

Abstract: Memory device and methods for controlling the memory device include an input buffer of the memory device receives input data from external to the memory device and outputs serial data. A serial shift register that shifts in the serial data and to output the serial data in a parallel format as parallel data. A parallel register that receives the parallel data from the serial shift register and buffered data directly from the input buffer. The parallel register that passes the parallel data and the buffered data to a data write bus to be stored memory banks of the memory device. Serial-to-parallel conversion circuitry controls loading of the parallel register from the serial shift register and the input buffer. The serial-to-parallel conversion circuitry utilizes a first loading signal to load the buffered data into the parallel register and a second loading signal to load the parallel data into the parallel register.

公开(公告)号：US20190228808A1

公开(公告)日：2019-07-25

申请号：US15875651

申请日：2018-01-19

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C7/10 ,  G06F13/16 ,  G06F1/08 ,  G11C8/12 ,  G11C7/22

Abstract: Methods and systems for internal timing schemes are provided. A data strobe (DQS) signal is received at a memory device. The DQS signal is shifted in a negative direction relative to a clock of the memory device to cause a fail point of a flip flop of the memory device. After causing the fail point, the DQS signal is shifted in a positive direction relative to the clock. A transition edge of an internal write signal (IWS) is centered in a DQS period, such as a write preamble. The IWS indicates that a write command is to be captured. Moreover, centering the transition edge includes selectively delaying the IWS in the negative direction.

公开(公告)号：US20190189184A1

公开(公告)日：2019-06-20

申请号：US16200460

申请日：2018-11-26

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4096 ,  G11C2207/105

Abstract: Devices and methods include receiving write command at a command interface of the semiconductor device to write data to memory. An external data strobe is received at a data strobe pin of the semiconductor device. The received external data strobe is divided into multiple phases using phase division circuitry to divide the data strobe into multiple phases to be used in writing the data to the memory.

公开(公告)号：US20190109587A1

公开(公告)日：2019-04-11

申请号：US15730233

申请日：2017-10-11

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: H03K3/037 ,  G11C7/10 ,  G06F13/16

Abstract: Memory devices may receive data from data processing devices for storage and processing during write operations. The received data may be accompanied by a data strobing signal that informs the memory device that data available in the bus is ready for latching. The data strobing signal may be provided via a tri-stateable or bidirectional connection and, as a result, during initialization of a write operation, the input circuitry may suffer from metastability during an initial transient period. The present application discusses methods and systems that may mitigate metastability by preventing invalid states in the input circuitry when data strobing signal is invalid or disabled. Certain embodiments determine if the data strobing signal is a valid input and, accordingly, adjust the received signal to a fixed value or to a previously received value. The use of latches and differential amplifiers to perform these functions is also discussed.

公开(公告)号：US10176862B1

公开(公告)日：2019-01-08

申请号：US15880994

申请日：2018-01-26

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney

IPC: G11C7/00 ,  G11C11/4076 ,  G06F11/10 ,  G11C11/4096

Abstract: Methods and devices for gating an internal data strobe from an input buffer of a memory device. The gating function occurs after a write operation ceases but before an external controller stops driving an external data strobe that is used to generate the internal data strobe. The methods and devices use local counters to count how many pulses have occurred on the data strobe during a write operation. When the local counters indicate that an expected number of cycles for the write operation have elapsed, the local counters indicate that the write operation has completed. This indication causes gating circuitry to cut off the internal data strobe from writing circuitry.