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公开(公告)号：US20210374061A1
公开(公告)日：2021-12-02
申请号：US16883769
申请日：2020-05-26
Applicant: Micron Technology, Inc.
Inventor： Crescenzo Attanasio , Massimo Iaculo , Pasquale Cimmino , Nicola Cavaliere , Francesco Falanga
IPC: G06F12/0875 , G06F9/30
Abstract: Methods, systems, and devices for an enhanced instruction caching scheme are described. A memory controller may include a first closely-coupled memory component that is associated with storing data and control information and a second closely-coupled memory component that is associated with storing control information. The memory controller may be configured to retrieve data from the first memory closely-coupled component and control information from a second closely-coupled memory component. Control information may be stored in the first closely-coupled memory component, and a memory controller may access the control information stored in the first closely-coupled memory component by transferring, from the first closely-coupled memory component, the control information into the second closely-coupled memory component. After transferring the control information into the second closely-coupled memory component, the memory controller may access the control information from the second closely-coupled memory component.
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公开(公告)号：US10282102B2
公开(公告)日：2019-05-07
申请号：US15131447
申请日：2016-04-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Francesco Falanga , Danilo Caraccio
Abstract: A host that is coupled to a memory device is configured to read a status register of the memory device to determine if the memory device supports host controlled enablement of automatic background operations. The memory device responds to the host regarding whether the memory device supports host controlled enablement of automatic background operations. The host can enable the automatic background operations if the memory device supports this feature. The host can then set a time period in the memory device that is indicative of when the memory device can automatically perform the background operations.
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公开(公告)号：US20190121575A1
公开(公告)日：2019-04-25
申请号：US15790690
申请日：2017-10-23
Applicant: Micron Technology, Inc.
Inventor： Angelo Della Monica , Eric Kwok Fung Yuen , Pasquale Cimmino , Massimo Iaculo , Francesco Falanga
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0632 , G06F3/0644 , G06F3/0679
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
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公开(公告)号：US09552895B2
公开(公告)日：2017-01-24
申请号：US14552863
申请日：2014-11-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Francesco Falanga , Victor Tsai
CPC classification number: G11C29/38 , G11C16/0483 , G11C16/3418 , G11C29/36 , G11C29/4401 , G11C29/52 , G11C2029/0407 , G11C2029/0409
Abstract: Memory devices storing particular data, systems containing such memory devices and methods of testing such memory devices. The memory devices include an array of memory cells containing particular data, and control circuitry configured to control operations of the array of memory cells. The control circuitry is further configured to perform a test of the particular data in response to a command received from an external device and perform a repair of the particular data when results of the test indicate that repair of the particular data is needed
Abstract translation: 存储特定数据的存储器件，包含这种存储器件的系统以及测试这样的存储器件的方法。 存储器件包括包含特定数据的存储器单元的阵列，以及被配置为控制存储器单元阵列的操作的控制电路。 控制电路还被配置为响应于从外部设备接收的命令来执行特定数据的测试，并且当测试结果指示需要修复特定数据时执行特定数据的修复
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公开(公告)号：US20240419353A1
公开(公告)日：2024-12-19
申请号：US18750250
申请日：2024-06-21
Applicant: Micron Technology, Inc.
Inventor： Francesco Basso , Antonino Pollio , Francesco Falanga , Massimo Iaculo
IPC: G06F3/06
Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.
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Patent Agency Ranking
公开(公告)号：US11966752B2
公开(公告)日：2024-04-23
申请号：US17645685
申请日：2021-12-22
Applicant: Micron Technology, Inc.
Inventor： Francesco Basso , Giuseppe Ferrari , Francesco Falanga , Massimo Iaculo
IPC: G06F9/44 , G06F9/4401 , G06F12/0871
CPC classification number: G06F9/4406 , G06F12/0871
Abstract: Methods, systems, and devices for data caching for fast system boot-up are described. A memory system may create a linked mapping of addresses, which may also be referred to as a mixed page pointer table. The linked mapping may include logical addresses associated with commands received during a boot-up procedure, and their associated physical addresses. The linked mapping may also include a counter associated with each logical address to track how often the logical address is referenced during successive boot-up procedures. Over successive boot-up procedures, addresses may be added or removed from the linked mapping, and sequential addresses may be compressed. The memory device may use the linked mapping to predict which data may be accessed during the boot-up procedure, and may pre-transfer the data to volatile memory based on the prediction.
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公开(公告)号：US20240069784A1
公开(公告)日：2024-02-29
申请号：US17900361
申请日：2022-08-31
Applicant: Micron Technology, Inc.
Inventor： Francesco Basso , Antonino Pollio , Francesco Falanga , Massimo Iaculo
IPC: G06F3/06
CPC classification number: G06F3/0653 , G06F3/0604 , G06F3/0652 , G06F3/0679
Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.
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公开(公告)号：US20230195475A1
公开(公告)日：2023-06-22
申请号：US17645687
申请日：2021-12-22
Applicant: Micron Technology, Inc.
Inventor： Francesco Basso , Luca Porzio , Roberto Izzi , Francesco Falanga , Nadav Grosz , Massimo Iaculo
IPC: G06F9/4401 , G06F3/06
CPC classification number: G06F9/4406 , G06F3/0644 , G06F3/061 , G06F3/0683
Abstract: Methods, systems, and devices for data defragmentation for a system boot procedure are described. The memory system may determine a write random index associated with a boot procedure. The write random index may indicate a relationship between a first quantity of sequential logical addresses accessed as part of the boot procedure and a second quantity of random logical addresses accessed as part of the boot procedure. The memory system may determine whether the write random index satisfies a threshold based on determining the write random index. In some cases, the memory system may transfer, to a second portion of the memory system, data stored in a first portion of the memory system based on determining that the write random index satisfies the threshold. The memory system may receive a request to perform the boot procedure after transferring the data and output, to the host system, the data transferred.
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公开(公告)号：US20220197504A1
公开(公告)日：2022-06-23
申请号：US17692241
申请日：2022-03-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Francesco Falanga , Danilo Caraccio
Abstract: Memory devices might include an array of memory cells, a register, and a controller for access of the array of memory cells. The controller might be configured to autonomously perform background operations on the array of memory cells in response to the register storing a first value, and prohibit autonomous performance of the background operations on the array of memory cells in response to the register storing a second value different than the first value. The memory devices might be in communication with a host.
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公开(公告)号：US20200371719A1
公开(公告)日：2020-11-26
申请号：US16990864
申请日：2020-08-11
Applicant: Micron Technology, Inc.
Inventor： Angelo Della Monica , Eric Kwok Fung Yuen , Pasquale Cimmino , Massimo Iaculo , Francesco Falanga
IPC: G06F3/06
Abstract: A variety of applications can include apparatus and/or methods of operating the apparatus in which functionalities of a memory device of the apparatus can be extended by changing data flow behaviour associated with standard commands used between a host platform and the memory device. Such functionalities can include debug capabilities. In an embodiment, a standard write command and data using a standard protocol to write to a memory device is received in the memory device, where the data is setup information to enable an extension component in the memory device. An extension component includes instructions in the memory device to execute operations on components of the memory device. The memory device can execute operations of the enabled extension component in the memory device based on the setup information. Additional apparatus, systems, and methods are disclosed.
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