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    Interconnect structure with nitrided barrier
    14.
    发明授权
    Interconnect structure with nitrided barrier 有权

    公开(公告)号：US10403575B2

    公开(公告)日：2019-09-03

    申请号：US15405711

    申请日：2017-01-13

    Applicant: Micron Technology, Inc.

    Inventor： Gregory C. Herdt ,  Mikhail A. Treger ,  Jin Lu

    IPC: H01L23/48 ,  H01L23/532 ,  H01L21/768

    Abstract: Semiconductor device interconnect structures comprising nitrided barriers are disclosed herein. In one embodiment, an interconnect structure includes a conductive material at least partially filling an opening in a semiconductor substrate, and a nitrided barrier between the conductive material and a sidewall in the opening. The nitrided barrier comprises a nitride material and a barrier material, such as tantalum, between the nitride material and the sidewall of the substrate.

    Semiconductor Constructions and Methods of Forming Intersecting Lines of Material
    17.
    发明申请
    Semiconductor Constructions and Methods of Forming Intersecting Lines of Material 有权
    形成相交线材料的半导体结构和方法

    公开(公告)号：US20160293482A1

    公开(公告)日：2016-10-06

    申请号：US15182462

    申请日：2016-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Gowrisankar Damarla ,  Robert J. Hanson ,  Jin Lu ,  Shyam Ramalingam

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

    Abstract translation: 一些实施例包括具有在交叉点处彼此相交的第一和第二导电线的半导体结构。 第一线主要具有第一宽度，并且具有直接相对于第二线并且在第二线的相对侧彼此变窄的区域。 导电触头沿着第一线并且直接电耦合到第一线，并且一个导电触头直接抵靠该交叉。 一些实施例包括形成相交线材料的方法。 形成第一和第二沟槽，并在相交处相互交叉。 第一沟槽主要具有第一宽度，并且将区域直接靠在第二沟槽和第二沟槽的相对侧上彼此变窄。 材料沉积在第一和第二沟槽内，以基本上完​​全填充第一和第二沟槽。

    Semiconductor constructions
    18.
    发明授权
    Semiconductor constructions 有权
    半导体结构

    公开(公告)号：US09391001B2

    公开(公告)日：2016-07-12

    申请号：US13975722

    申请日：2013-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Gowrisankar Damarla ,  Robert J. Hanson ,  Jin Lu ,  Shyam Ramalingam

    IPC: H01L23/48 ,  H01L29/00 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection. The first line has primarily a first width, and has narrowed regions directly against the second line and on opposing sides of the second line from one another. Electrically conductive contacts are along the first line and directly electrically coupled to the first line, and one of the electrically conductive contacts is directly against the intersection. Some embodiments include methods of forming intersecting lines of material. First and second trenches are formed, and intersect with one another at an intersection. The first trench has primarily a first width, and has narrowed regions directly against the second trench and on opposing sides of the second trench from one another. Material is deposited within the first and second trenches to substantially entirely fill the first and second trenches.

    Abstract translation: 一些实施例包括具有在交叉点处彼此相交的第一和第二导电线的半导体结构。 第一线主要具有第一宽度，并且具有直接相对于第二线并且在第二线的相对侧彼此变窄的区域。 导电触头沿着第一线并且直接电耦合到第一线，并且一个导电触头直接抵靠该交叉。 一些实施例包括形成相交线材料的方法。 形成第一和第二沟槽，并在相交处相互交叉。 第一沟槽主要具有第一宽度，并且将区域直接靠在第二沟槽和第二沟槽的相对侧上彼此变窄。 材料沉积在第一和第二沟槽内，以基本上完​​全填充第一和第二沟槽。

    INTERCONNECT ASSEMBLIES WITH THROUGH-SILICON VIAS AND STRESS-RELIEF FEATURES
    19.
    发明申请
    INTERCONNECT ASSEMBLIES WITH THROUGH-SILICON VIAS AND STRESS-RELIEF FEATURES 审中-公开
    通过硅橡胶和应力消除特征的互连组件

    公开(公告)号：US20150243583A1

    公开(公告)日：2015-08-27

    申请号：US14188367

    申请日：2014-02-24

    Applicant: Micron Technology, Inc.

    Inventor： Hongqi Li ,  Anurag Jindal ,  Jin Lu ,  Gowrisankar Damarla ,  Shyam Ramalingam

    IPC: H01L23/48 ,  H01L21/768 ,  H01L23/367

    CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76847 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.

    Abstract translation: 根据一些实施例的半导体器件包括延伸穿过衬底结构的至少一部分的衬底结构和导电互连。 导电互连可以包括通过硅通孔和应力消除特征，其适应材料的热膨胀和/或热收缩以管理半导体器件中的内部应力。 根据一些实施例的制造半导体器件的方法包括去除导电互连的材料以形成应力消除间隙。

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