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公开(公告)号：US10811101B2
公开(公告)日：2020-10-20
申请号：US16537345
申请日：2019-08-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Yafeng Zhang , Liang Qiao , Chunyuan Hou , Jun Xu
Abstract: Apparatuses and methods for protecting transistors through charge sharing are disclosed herein. An example apparatus includes a transistor comprising a gate node and a bulk node, a charge sharing circuit coupled between the gate and bulk nodes, and logic. The charge sharing circuit is configure to equalize charge differences between the gate and bulk nodes, and the logic is configured to enable the charge sharing circuit based at least in part on a combination of first and second signals, which indicate the presence of a condition.
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12.发明申请公开(公告)号：US20190287619A1
公开(公告)日：2019-09-19
申请号：US16433193
申请日：2019-06-06
Applicant: Micron Technology, Inc.
Abstract: Methods include incrementing a first read count in response to performing a read operation on a memory cell of a block of memory cells, the first read count corresponding to a first portion of memory cells of the block of memory cells; incrementing a second read count in response to performing the read operation on the memory cell of the block of memory cells, the second read count corresponding to a second portion of memory cells of the block of memory cells; resetting the first read count in response to performing an erase operation on the first portion of memory cells of the block of memory cells; and resetting the second read count in response to performing an erase operation on the second portion of memory cells of the block of memory cells.
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公开(公告)号：US12276686B2
公开(公告)日：2025-04-15
申请号：US17894227
申请日：2022-08-24
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dan Xu , Jun Xu , Erwin E. Yu
Abstract: Apparatus having an array of memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to apply a reference current to a selected access line, determine a time difference between a voltage level of a near end of the selected access line being deemed to exceed a first voltage level while applying the reference current and the voltage level of the near end of the selected access line being deemed to exceed a second voltage level while applying the reference current, and determine a capacitance value of the selected access line in response to a current level of the reference current, the time difference, and a voltage difference between the second voltage level and the first voltage level.
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公开(公告)号：US11694753B2
公开(公告)日：2023-07-04
申请号：US17718435
申请日：2022-04-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu
IPC: G11C16/26 , G11C16/12 , G11C16/30 , G11C16/34 , H03K19/17728
CPC classification number: G11C16/26 , G11C16/12 , G11C16/30 , G11C16/3404 , H03K19/17728
Abstract: Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.
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公开(公告)号：US20230078401A1
公开(公告)日：2023-03-16
申请号：US17989168
申请日：2022-11-17
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Violante Moschiano , Erwin E. Yu
Abstract: A programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. A program verify operation is caused to be performed on the memory cell to determine that a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node associated with the memory cell. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell to reduce a rate of programming associated with the memory cell.
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Patent Agency Ranking
公开(公告)号：US11532367B2
公开(公告)日：2022-12-20
申请号：US17115357
申请日：2020-12-08
Applicant: Micron Technology, Inc.
Inventor： Jun Xu , Violante Moschiano , Erwin E. Yu
Abstract: A first programming pulse is caused to be applied to a wordline associated with a memory cell of the memory sub-system. In response to first programming pulse, causing a program verify operation to be performed to determine a measured threshold voltage associated with the memory cell. The measured threshold voltage associated with the memory cell is stored in a sensing node. A determination is made that the measured threshold voltage of the memory cell satisfies a condition and the measured threshold voltage stored in the sensing node is identified. A bitline voltage matching the measured threshold voltage is caused to be applied to a bitline associated with the memory cell.
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公开(公告)号：US20220238165A1
公开(公告)日：2022-07-28
申请号：US17718435
申请日：2022-04-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu
IPC: G11C16/26 , G11C16/12 , G11C16/30 , H03K19/17728 , G11C16/34
Abstract: Memory might include a controller configured to cause the memory to capacitively couple a first voltage level from a voltage node to a node of a sense circuit, selectively discharge the node of the sense circuit through a memory cell, measure a current demand of the voltage node while selectively discharging the node of the sense circuit through the memory cell, determine a second voltage level in response to the measured current demand, isolate the node of the sense circuit from the memory cell, capacitively couple the second voltage level from the voltage node to the node of the sense circuit, and determine a data state of the memory cell in response to a voltage level of the node of the sense circuit while capacitively coupling the second voltage level to the node of the sense circuit.
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公开(公告)号：US20220130475A1
公开(公告)日：2022-04-28
申请号：US17568797
申请日：2022-01-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu , Yingda Dong
Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.
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公开(公告)号：US11238946B2
公开(公告)日：2022-02-01
申请号：US17078161
申请日：2020-10-23
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jun Xu , Yingda Dong
Abstract: A memory might include a common source, a first data line and a second data line, an array of memory cells, a plurality of access lines, and a controller. The array of memory cells might include a first string of memory cells selectively connected between the first data line and the common source and a second string of memory cells selectively connected between the second data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of the first string of memory cells and a control gate of a respective memory cell of the second string of memory cells. The controller may access the array of memory cells. The controller might be configured to implement a source-side seeding operation concurrently with a data line set operation.
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20.发明申请公开(公告)号：US20210201993A1
公开(公告)日：2021-07-01
申请号：US17011018
申请日：2020-09-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Dan Xu , Jun Xu , Erwin E. Yu , Paolo Tessariol , Tomoko Ogura Iwasaki
IPC: G11C13/00
Abstract: Memory array structures providing for determination of resistive characteristics of access lines might include a first block of memory cells, a second block of memory cells, a first current path between a particular access line of the first block of memory cells and a particular access line of the second block of memory cells, and, optionally, a second current path between the particular access line of the second block of memory cells and a different access line of the first block of memory cells. Methods for determining resistive characteristics of access lines might include connecting the particular access line of the first block of memory cells to a driver, and determining the resistive characteristics in response to a current level through that access line and a voltage level of that access line.
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