公开(公告)号：US12200928B2

公开(公告)日：2025-01-14

申请号：US17387669

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Albert Fayrushin ,  Yingda Dong

IPC: H10B43/27 ,  H01L21/28 ,  H01L29/423 ,  H10B41/27

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.

公开(公告)号：US11791003B2

公开(公告)日：2023-10-17

申请号：US17960252

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3481 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US11688476B2

公开(公告)日：2023-06-27

申请号：US17568797

申请日：2022-01-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Xu ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5621

Abstract: A device might include a common source, a three-dimensional array of memory cells, a plurality of access lines, and a controller. The three-dimensional array of memory cells might include a plurality of NAND strings. Each NAND string might be selectively connected between a corresponding data line and the common source. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each NAND string of the plurality of NAND strings. The controller might be configured to access the three-dimensional array of memory cells to implement a source-side seeding operation.

公开(公告)号：US20230197164A1

公开(公告)日：2023-06-22

申请号：US18076537

申请日：2022-12-07

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Yingda Dong ,  Ching-Huang Lu

IPC: G11C16/12 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

CPC classification number: G11C16/12 ,  G11C16/28 ,  G11C16/08 ,  G11C16/30

Abstract: Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.

公开(公告)号：US20220199175A1

公开(公告)日：2022-06-23

申请号：US17249433

申请日：2021-03-02

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/30 ,  G11C16/10 ,  G11C16/08

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20210391024A1

公开(公告)日：2021-12-16

申请号：US16946273

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.

公开(公告)号：US20250037773A1

公开(公告)日：2025-01-30

申请号：US18781618

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Xiangyu Yang ,  Yingda Dong

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatuses, systems, and methods for applying a read voltage overdrive. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a pass voltage to a wordline in the array of memory cells, apply a read voltage to the wordline, and apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the wordline.

公开(公告)号：US11967387B2

公开(公告)日：2024-04-23

申请号：US17970459

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Q. Diep ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30

Abstract: Processing logic in a memory device initiates a program operation on a memory array, the program operation comprising a program phase and a program verify phase. The processing logic further causes a negative voltage signal to be applied to a first selected word line of a block of the memory array during the program verify phase of the program operation, wherein the first selected word line is coupled to a corresponding first memory cell of a first plurality of memory cells in a string of memory cells in the block, wherein the first selected word line is associated with the program operation.

公开(公告)号：US20240120010A1

公开(公告)日：2024-04-11

申请号：US18545888

申请日：2023-12-19

Applicant: Micron Technology, Inc.

Inventor： Vinh Q. Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32

Abstract: Control logic in a memory device initiates a program operation on a memory array, the program operation comprising a seeding phase. During the seeding phase, the control logic causes a seeding voltage to be applied to a string of memory cells in a data block of the memory array during the seeding phase of the program operation and causes a first positive voltage to be applied to a first plurality of word lines of the data block during the seeding phase, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in the string of memory cells, the first plurality of word lines comprising a selected word line associated with the program operation. The control logic further causes a second positive voltage to be applied to one or more second word lines coupled to one or more second memory cells on a source-side of the first plurality of memory cells in the string of memory cells during the seeding phase, wherein the second positive voltage is less than the first positive voltage.

公开(公告)号：US20240071515A1

公开(公告)日：2024-02-29

申请号：US18235183

申请日：2023-08-17

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Vinh Quang Diep ,  Avinash Rajagiri ,  Yingda Dong

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483

Abstract: Control logic of a memory device to initiate an erase operation including a set of erase loops to erase one or more memory cells of the memory device. During a first erase loop of the set of erase loops, a first erase pulse having an erase voltage level is caused to be applied to a source line associated with the one or more memory cells. During the first erase loop, a first erase bias voltage having an initial voltage level is caused to be applied to a first select gate and a second erase bias voltage having the initial voltage level is caused to be applied to a second select gate associated with the source line, where the first erase bias voltage level is based on a first delta voltage level. During a subset of erase loops following the first erase loop, a second erase pulse having the erase voltage level is caused to be applied to the source line. During the subset of erase loops, a first adjusted erase bias voltage is caused to be applied to the first select gate and a second adjusted erase bias voltage is caused to be applied to the second select gate.