公开(公告)号：US20210217475A1

公开(公告)日：2021-07-15

申请号：US17218243

申请日：2021-03-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06

Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.

公开(公告)号：US20210183452A1

公开(公告)日：2021-06-17

申请号：US17189529

申请日：2021-03-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

Abstract: A memory device might include control circuitry configured to cause the memory device to compare input data to data stored in memory cells connected to a data line, cause a first level of current to flow from the data line in response to a mismatch between one digit of the input data and data stored in a respective pair of memory cells, cause a second level of current to flow from the data line in response to a mismatch between a different digit of the input data and the data stored in a respective pair of memory cells, compare a representation of a level of current in the data line to a reference, and deem the input data to potentially match or not match the data stored in the plurality of memory cells in response to the comparison.

公开(公告)号：US10984864B2

公开(公告)日：2021-04-20

申请号：US16517846

申请日：2019-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US10395740B2

公开(公告)日：2019-08-27

申请号：US16003357

申请日：2018-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26

Abstract: Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.

公开(公告)号：US20190050162A1

公开(公告)日：2019-02-14

申请号：US16166231

申请日：2018-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

IPC: G06F3/06 ,  G11C11/00 ,  G11C15/04 ,  G06F11/22 ,  G11C16/04 ,  G06F11/10

CPC classification number: G06F3/0634 ,  G06F3/0626 ,  G06F3/0632 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/1064 ,  G06F11/2263 ,  G11C11/005 ,  G11C15/046 ,  G11C16/0483

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

公开(公告)号：US20180108415A1

公开(公告)日：2018-04-19

申请号：US15841490

申请日：2017-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US20170309341A1

公开(公告)日：2017-10-26

申请号：US15645009

申请日：2017-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.

公开(公告)号：US09595334B2

公开(公告)日：2017-03-14

申请号：US15163927

申请日：2016-05-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C16/10 ,  G06F12/02 ,  G11C16/34 ,  G11C11/56 ,  G11C15/04 ,  G11C16/04 ,  G06F7/02 ,  G11C16/26 ,  G11C16/12 ,  G11C16/14

CPC classification number: G11C16/10 ,  G06F7/02 ,  G06F12/0246 ,  G06F2207/00 ,  G06F2207/025 ,  G11C11/56 ,  G11C11/5628 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the memory cells to a respective data state of three or more data states, searching for an exact match to a particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells only when the value of the attribute is the particular value, and searching for an inexact match to the particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells when the value of the attribute is within a range of possible values of the attribute including the particular value.

Abstract translation: 操作存储器的装置和方法包括通过将每个存储器单元编程为三个或更多数据状态的相应数据状态来将特征向量的属性的值存储到一对存储器单元，搜索与 通过将属性的各个电压电平施加到控制存储器单元的栅极以仅仅在属性的值是特定值才激活两个存储器单元，并通过应用相应的值来搜索与特定值的不精确匹配的属性的特定值 当属性的值在包括特定值的属性的可能值的范围内时，控制存储器单元的栅极的电压电平来激活两个存储器单元。

公开(公告)号：US20160267993A1

公开(公告)日：2016-09-15

申请号：US15163927

申请日：2016-05-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F7/02 ,  G06F12/0246 ,  G06F2207/00 ,  G06F2207/025 ,  G11C11/56 ,  G11C11/5628 ,  G11C15/046 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34

Abstract: Apparatus and methods of operating a memory include storing a value of an attribute of a feature vector to a pair of memory cells by programming each of the memory cells to a respective data state of three or more data states, searching for an exact match to a particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells only when the value of the attribute is the particular value, and searching for an inexact match to the particular value of the attribute by applying respective voltage levels to control gates of the memory cells to activate both memory cells when the value of the attribute is within a range of possible values of the attribute including the particular value.

Abstract translation: 操作存储器的装置和方法包括通过将每个存储器单元编程为三个或更多数据状态的相应数据状态来将特征向量的属性的值存储到一对存储器单元，搜索与 通过将属性的各个电压电平施加到控制存储器单元的栅极以仅仅在属性的值是特定值才激活两个存储器单元，并通过应用相应的值来搜索与特定值的不精确匹配的属性的特定值 当属性的值在包括特定值的属性的可能值的范围内时，控制存储器单元的栅极的电压电平来激活两个存储器单元。

公开(公告)号：US20150318047A1

公开(公告)日：2015-11-05

申请号：US14798845

申请日：2015-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells.

Abstract translation: 公开了存储器件和方法。 一种这样的方法将输入数据与存储器件中的存储数据进行比较，并且包括将第一加权因子应用于耦合到数据线的存储器单元的第一串，其中存储的数据的第一位被存储在第一存储单元串中 ; 将第二加权因子应用于耦合到所述数据线的第二存储单元串，其中存储数据的第二位存储在所述第二存储单元串中; 将第一加权因子应用于第一串存储器单元时，将第一比特的输入数据与存储数据的第一比较; 以及将所述输入数据的第二位与存储的数据的第二位进行比较，同时将所述第二权重因子应用于所述第二存储单元串。