公开(公告)号：US20210382511A1

公开(公告)日：2021-12-09

申请号：US16891963

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Si Hong Kim ,  Ki-Jun Nam

IPC: G05F1/613 ,  G11C11/4074 ,  G11C11/22 ,  H02M3/158 ,  G06F1/26

Abstract: An electronic device may include a main circuit including multiple sub-circuits powered by a direct-current (DC) power supply circuit. The main circuit has a main circuit current demand being a time-varying demand for a DC voltage-regulated supply current being a function of a number of the sub-circuits being active. The DC power supply circuit may include multiple DC voltage regulators to provide the main circuit with the supply current and a command decoding and power management circuit to control enablement of the voltage regulators. The command decoding and power management circuit may be configured to detect an instant value of the main circuit current demand and to selectively enable one or more of the voltage regulators based on the detected instant value.

公开(公告)号：US20210373648A1

公开(公告)日：2021-12-02

申请号：US16890819

申请日：2020-06-02

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Yantao Ma ,  Yasushi Matsubara ,  Takamasa Suzuki

IPC: G06F1/3296 ,  G11C11/22 ,  G06F1/3234

Abstract: Methods, systems, and devices for grouping power supplies for a power saving mode are described to configure a memory device with groups of internal power supplies whose voltage levels may be successively modified according to a group order signaled by an on-die timer. For example, when the memory device enters a deep sleep mode, respective voltage levels of a first group of internal power supplies may be modified to respective external power supply voltage levels at a first time, respective voltage levels of a second group of internal power supplies may be modified to respective external power supply voltage levels at a second time, and so on. When the memory device exits the deep sleep mode, the groups of internal voltage supplies may be modified from the respective external power supply voltage levels to respective operational voltage levels in a group order that is opposite to the entry group order.

公开(公告)号：US20230393645A1

公开(公告)日：2023-12-07

申请号：US17893946

申请日：2022-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ki-Jun Nam ,  Younghoon Oh

IPC: G06F1/3296 ,  G11C11/4074

CPC classification number: G06F1/3296 ,  G11C11/4074

Abstract: Apparatuses and methods for providing internal power voltages are described. An example apparatus includes a first, second, and third clamp circuits, and a clamp control circuit. The first clamp circuit is configured to receive a first external power voltage and provide a first voltage drop to provide a first internal power voltage. The second clamp circuit is configured to receive the first external power voltage and provide a second voltage drop to provide a second internal power voltage, wherein the first voltage drop is greater than the second voltage drop. The third clamp circuit is configured to receive a second external power voltage and provide the second external power voltage as the second internal power voltage when the second external power voltage is activated. The clamp control circuit is configured to activate the third clamp circuit when the second external power voltage reaches a trigger voltage level.

公开(公告)号：US11798634B2

公开(公告)日：2023-10-24

申请号：US17675622

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/12 ,  G11C7/20 ,  G11C16/04 ,  G11C16/32 ,  G11C11/4074 ,  G11C11/417

CPC classification number: G11C16/30 ,  G11C5/144 ,  G11C5/147 ,  G11C7/20 ,  G11C11/4074 ,  G11C11/417 ,  G11C16/045 ,  G11C16/12 ,  G11C16/32

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

公开(公告)号：US11176985B1

公开(公告)日：2021-11-16

申请号：US16925057

申请日：2020-07-09

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Hiroshi Akamatsu ,  Takamasa Suzuki ,  Yasushi Matsubara

IPC: G11C11/22 ,  G11C11/4074 ,  G06F11/30 ,  G11C5/14

Abstract: Apparatuses and methods related to power domain boundary protection in memory. A number of embodiments can include using a voltage detector to monitor a floating power supply voltage used to power a number of logic components while a memory device operates in a reduced power mode, and responsive to the voltage detector detecting that the floating power supply voltage reaches a threshold value while the memory device is in the reduced power mode, providing a control signal to protection logic to prevent a floating output signal driven from one or more of the logic components from being provided across a power domain boundary to one or more of a different number of logic components.

公开(公告)号：US20210350861A1

公开(公告)日：2021-11-11

申请号：US16870670

申请日：2020-05-08

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam ,  Takamasa Suzuki ,  Yantao Ma ,  Yasushi Matsubara

IPC: G11C16/30 ,  G11C16/12 ,  G11C16/32 ,  G11C16/04 ,  G11C7/20

Abstract: Methods, systems, and devices for sequential voltage control for a memory device are described. A memory device may have various voltage sources that support different voltage levels used in various operations of the memory device. Voltage sources of a memory device may be disabled under some circumstances, such as when the memory device is idled, or operated in a low-power or powered-down mode, among other circumstances. In accordance with examples as disclosed herein, voltage sources of a memory device or memory die may be sequentially enabled or sequentially disabled. For example, voltage sources may be enabled in an order from voltage sources having relatively higher nominal voltages to voltage sources having relatively lower voltages, or disabled in an order from voltage sources having relatively lower nominal voltages to voltage sources having relatively higher voltages.

公开(公告)号：US20210166753A1

公开(公告)日：2021-06-03

申请号：US17173048

申请日：2021-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiro Riho ,  Yoshinori Matsui ,  Kiyohiro Furutani ,  Takahiko Fukiage ,  Ki-Jun Nam ,  John D. Porter

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a memory cell array including a plurality of memory cells, a first counter circuit configured to periodically update a count value during a first operation mode, a burst clock generator configured to successively generate a burst pulse predetermined times When the count value indicates a predetermined value, and a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse.

公开(公告)号：US20240347102A1

公开(公告)日：2024-10-17

申请号：US18542581

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： William Chad Waldrop ,  Ki-Jun Nam ,  Won Joo Yun ,  Shingo Mitsubori

IPC: G11C11/4093

CPC classification number: G11C11/4093

Abstract: Systems and methods are provided for a memory device that includes a decision feedback equalizer (DFE) reset generator configured to transmit a DFE reset signal to reset taps of a DFE. The memory device also includes an input buffer. The input buffer includes a data branch configured to output data from the input buffer for use downstream in the memory device. The input buffer also includes a DFE reset branch configured to reset the taps for the DFE based on the DFE reset signal. Moreover, resetting the taps using the DFE reset branch does not reset output data of the data branch.

公开(公告)号：US12094521B2

公开(公告)日：2024-09-17

申请号：US17884261

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Ki-Jun Nam

IPC: G11C7/08 ,  G11C7/06 ,  G11C11/4091 ,  G11C7/22

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/08 ,  G11C7/227

Abstract: A memory device includes a memory cell that stores data. The memory device also includes a pair of digit lines that carry the data from the memory cell. The memory device further includes a sense amplifier that senses and amplifies voltages received at the pair of digit lines. The memory device also includes a replica sense amplifier that generates a replica common mode voltage associated with a common mode voltage of the pair of digit lines.

公开(公告)号：US20230178139A1

公开(公告)日：2023-06-08

申请号：US17922199

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Si Hong Kim ,  Ki-Jun Nam ,  Zhi Qi Huang ,  John David Porter

IPC: G11C11/4076

CPC classification number: G11C11/4076

Abstract: A system (100) for providing a timing signal with tunable temperature dependency in an electronic device may include a timing circuit (102) and an initial setting circuit (104). The timing circuit (102) may include a delay stage (106) and a gate stage (108). The delay stage (106) may be configured to receive an input signal and to produce a delayed signal by introducing a delay to the input signal. The gate stage (108) may be configured to receive the delayed signal and a threshold setting signal, to produce an output signal using the delayed signal and a logic threshold, and to set an initial value of the logic threshold according to the threshold setting signal. The initial setting circuit (104) may be configured to allow the threshold setting signal to be tuned for providing the time delay with a specified temperature dependency.