公开(公告)号：US20200118608A1

公开(公告)日：2020-04-16

申请号：US16436655

申请日：2019-06-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Akira Yamashita ,  Shuichi Murai ,  Kohei Nakamura

IPC: G11C7/22 ,  H03K5/15 ,  G11C11/4076

Abstract: Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

公开(公告)号：US10339998B1

公开(公告)日：2019-07-02

申请号：US15937552

申请日：2018-03-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Katsuhiro Kitagawa ,  Kazuhiro Kurihara ,  Kohei Nakamura ,  Akira Yamashita

IPC: G11C11/4076 ,  H03K5/1534 ,  H03K5/05 ,  H03K3/037 ,  H03K5/135 ,  H03K5/00

Abstract: Apparatuses and methods for providing clocks in a semiconductor device are disclosed. An example apparatus includes a clock generating circuit configured to generate an output clock signal based on one of rising and trailing edges of first, second, third and fourth clock signals in a first mode, phases of the first, second, third and fourth clock signals being shifted to each other. The clock generating circuit is further configured to generate the output clock signal based on both of rising and trailing edges of fifth and sixth clock signals in a second mode.

公开(公告)号：US09147446B2

公开(公告)日：2015-09-29

申请号：US14317978

申请日：2014-06-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kohei Nakamura

IPC: H03L5/00 ,  G11C7/10 ,  G11C5/14 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C7/1039 ,  G11C5/147 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4093

Abstract: Disclosed herein is a device includes: a level conversion circuit coupled to first and third power supply lines, receiving a first signal and an inverted signal of the first signal each having an amplitude between first and second potentials, and outputting a second signal having an amplitude between first and third potentials; a delay circuit coupled to the first and second power supply lines, and outputting a third signal delayed from the first signal; and an output circuit including first and second transistors coupled in series between the first and third power supply lines, the first transistor having a control electrode supplied with the second signal, and the second transistor having a control electrode supplied with the third signal.

Abstract translation: 本文公开了一种装置，包括：电平转换电路，耦合到第一和第三电源线，接收第一信号和第一信号的反相信号，每个信号具有第一和第二电位之间的幅度，并输出具有幅度的第二信号 第一和第三电位之间; 延迟电路，耦合到第一和第二电源线，并输出从第一信号延迟的第三信号; 以及输出电路，包括串联耦合在第一和第三电源线之间的第一和第二晶体管，第一晶体管具有提供有第二信号的控制电极，第二晶体管具有提供有第三信号的控制电极。

公开(公告)号：US20150022282A1

公开(公告)日：2015-01-22

申请号：US14331070

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Yuhei Kaneko ,  Kohei Nakamura

IPC: H03H11/28

CPC classification number: H03H11/28 ,  H03H7/38 ,  H03K17/6871

Abstract: An impedance adjustment circuit includes a counter circuit outputting a count value thereof as a plurality of first impedance adjustment signals, a mode selection circuit setting a second impedance adjustment signal to be in an active/inactive state irrespective of the count value, and a level fixing circuit fixing a third impedance adjustment signal to be in an active state. A pre-stage circuit generates a plurality of first output control signals, a second output control signal, and a third output control signal in response to the first impedance adjustment signals, the second impedance adjustment signal, and the third impedance adjustment signal, respectively, and a data signal. An output circuit includes a plurality of first transistors, a second transistor, and a third transistor connected in parallel to each other between an output terminal and a first power supply wiring. Control terminals of the first transistors, the second transistor, and the third transistor receive the first output control signals, the second output control signal, and the third output control signal, respectively.

Abstract translation: 阻抗调整电路包括将其计数值作为多个第一阻抗调整信号输出的计数器电路，将第二阻抗调整信号设定为处于活动/非活动状态而与计数值无关的模式选择电路，以及电平固定 电路将第三阻抗调整信号固定为处于活动状态。 响应于第一阻抗调整信号，第二阻抗调整信号和第三阻抗调节信号，预级电路分别产生多个第一输出控制信号，第二输出控制信号和第三输出控制信号， 和数据信号。 输出电路包括在输出端子和第一电源布线之间彼此并联连接的多个第一晶体管，第二晶体管和第三晶体管。 第一晶体管，第二晶体管和第三晶体管的控制端分别接收第一输出控制信号，第二输出控制信号和第三输出控制信号。