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公开(公告)号：US12079517B2
公开(公告)日：2024-09-03
申请号：US17870139
申请日：2022-07-21
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Peter Feeley , Jiangli Zhu , Fangfang Zhu , Akira Goda , Lakshmi Kalpana Vakati , Vivek Shivhare , Dave Scott Ebsen , Sanjay Subbarao
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.
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公开(公告)号：US12051479B2
公开(公告)日：2024-07-30
申请号：US17872567
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Akira Goda , Dave Scott Ebsen , Lakshmi Kalpana Vakati , Jiangli Zhu , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Fangfang Zhu
CPC classification number: G11C29/52 , G11C29/022
Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.
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公开(公告)号：US11977778B2
公开(公告)日：2024-05-07
申请号：US17691014
申请日：2022-03-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Eric N. Lee , Jeffrey S. McNeil , Jonathan S. Parry , Lakshmi Kalpana Vakati
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/064 , G06F3/0679
Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
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Patent Agency Ranking
公开(公告)号：US11907066B2
公开(公告)日：2024-02-20
申请号：US17734444
申请日：2022-05-02
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Jianmin Huang , Lakshmi Kalpana Vakati , Harish R. Singidi
CPC classification number: G06F11/1076 , G06F3/0619 , G06F3/0659 , G06F3/0673
Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.
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公开(公告)号：US20240028259A1
公开(公告)日：2024-01-25
申请号：US17870139
申请日：2022-07-21
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Peter Feeley , Jiangli Zhu , Fangfang Zhu , Akira Goda , Lakshmi Kalpana Vakati , Vivek Shivhare , Dave Scott Ebsen , Sanjay Subbarao
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.
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16.发明公开公开(公告)号：US20230367680A1
公开(公告)日：2023-11-16
申请号：US18143937
申请日：2023-05-05
Applicant: Micron Technology, Inc.
Inventor： Lu Tong , Ashish Ghai , Chai Chuan Yao , Ekamdeep Singh , Lakshmi Kalpana Vakati , Sheng Huang Lee , Matthew Ivan Warren , Dheeraj Srinivasan , Jeffrey Ming-Hung Tsai
CPC classification number: G06F11/2023 , G06F3/0617 , G06F3/064 , G06F3/0673 , G06F2201/805
Abstract: Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.
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公开(公告)号：US20230305744A1
公开(公告)日：2023-09-28
申请号：US17691014
申请日：2022-03-09
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Kishore Kumar Muchherla , Eric N. Lee , Jeffrey S. McNeil , Jonathan S. Parry , Lakshmi Kalpana Vakati
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0619 , G06F3/064 , G06F3/0679
Abstract: A method performed by a processing device receives a plurality of write operation requests, where each of the write operation requests specifies a respective one of the memory units, identifies one or more operating characteristic values, where each operating characteristic value reflects one or more memory access operations performed on a memory device, and determines whether the operating characteristic values satisfy one or more threshold criteria. Responsive to determining that the operating characteristic values satisfy the one or more threshold criteria, the method performs a plurality of write operations, where each of the write operations writes data to the respective one of the memory units, and performs a multiple-read scan operation subsequent to the plurality of write operations, where the multiple-read scan operation reads data from each of the memory units.
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公开(公告)号：US20220261313A1
公开(公告)日：2022-08-18
申请号：US17734444
申请日：2022-05-02
Applicant: Micron Technology, Inc.
Inventor： Xiangang Luo , Jianmin Huang , Lakshmi Kalpana Vakati , Harish R. Singidi
Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.
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