公开(公告)号：US20180137922A1

公开(公告)日：2018-05-17

申请号：US15350229

申请日：2016-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.

公开(公告)号：US20210134373A1

公开(公告)日：2021-05-06

申请号：US17149048

申请日：2021-01-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/20 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/32 ,  H01L27/115

Abstract: Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

公开(公告)号：US20190066771A1

公开(公告)日：2019-02-28

申请号：US15688645

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US10049750B2

公开(公告)日：2018-08-14

申请号：US15350229

申请日：2016-11-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Koji Sakui ,  Mark Hawes ,  Toru Tanzawa ,  Jeremy Binfet

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/14

Abstract: Apparatus and methods of operating such apparatus include establishing a negative potential in a body of a memory cell prior to initiating a sensing operation on the memory cell, in response to a timer, or during an access operation of another memory cell.