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    POWER MANAGEMENT ACROSS MULTIPLE PACKAGES OF MEMORY DIES
    1.
    发明申请
    POWER MANAGEMENT ACROSS MULTIPLE PACKAGES OF MEMORY DIES 有权

    公开(公告)号：US20230089479A1

    公开(公告)日：2023-03-23

    申请号：US17993194

    申请日：2022-11-23

    Applicant: Micron Technology, Inc.

    Inventor： Liang Yu ,  Jeremy Wayne Butterfield ,  Jeremy Binfet

    IPC: G11C11/4074 ,  G11C11/4076 ,  G11C5/14 ,  G11C5/06 ,  G11C11/409

    Abstract: A variety of applications can include multiple memory die packages configured to engage in peak power management (PPM) across the multiple packages of memory dies. A communication line coupled to each memory die in the multiple memory die packages can be used to facilitate the PPM. A global management die can start a communication sequence among the multiple memory die packages to share a current budget across the multiple memory die packages by driving a signal on the communication line. Local management dies can use the received signal having clock pulses driven by the global management die on the communication line to engage in the PPM. To engage in global PPM, each memory die can be structured, to be selected as the global management die or a local management die, with one or more controllers to interface with the multiple memory die packages and to handle current budget limits.

    MEMORY ACCESS MANAGMENT
    2.
    发明申请
    MEMORY ACCESS MANAGMENT 有权

    公开(公告)号：US20230063057A1

    公开(公告)日：2023-03-02

    申请号：US17458835

    申请日：2021-08-27

    Applicant: Micron Technology, Inc.

    Inventor： Eric N. Lee ,  Robert W. Strong ,  William Akin ,  Jeremy Binfet

    IPC: G06F3/06

    Abstract: A method includes detecting an occurrence of an event associated with a memory sub-system comprising blocks of non-volatile memory cells. The method further includes responsive to detecting the occurrence of the event, providing signaling to disable at least a portion of the memory sub-system, an interface coupled to the memory sub-system, or both.

    POWER ARCHITECTURE FOR NON-VOLATILE MEMORY
    4.
    发明申请
    POWER ARCHITECTURE FOR NON-VOLATILE MEMORY 有权

    公开(公告)号：US20230017388A1

    公开(公告)日：2023-01-19

    申请号：US17873850

    申请日：2022-07-26

    Applicant: Micron Technology, Inc.

    Inventor： Qisong Lin ,  Shuai Xu ,  Jonathan S. Parry ,  Jeremy Binfet ,  Micheie Piccardi ,  Qing Liang

    IPC: G11C16/30 ,  G06F3/06 ,  G06F12/0875 ,  G11C16/10

    Abstract: Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.

    SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY
    5.
    发明申请
    SEPARATE PARTITION FOR BUFFER AND SNAPSHOT MEMORY 有权

    公开(公告)号：US20220350517A1

    公开(公告)日：2022-11-03

    申请号：US17846462

    申请日：2022-06-22

    Applicant: Micron Technology, Inc.

    Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, JR. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

    IPC: G06F3/06

    Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

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