公开(公告)号：US20190066771A1

公开(公告)日：2019-02-28

申请号：US15688645

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US20180233200A1

公开(公告)日：2018-08-16

申请号：US15954282

申请日：2018-04-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20160180934A1

公开(公告)日：2016-06-23

申请号：US14971634

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 本文公开的各种实施例包括通过响应于流过所选择的串的读取电流到数据线来感测逻辑电平来读取所选择的存储器串中的所选择的存储器单元中的逻辑电平的装置和方法。 公开了附加装置，系统和方法。

公开(公告)号：US20150170756A1

公开(公告)日：2015-06-18

申请号：US14632556

申请日：2015-02-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.

Abstract translation: 一些实施例包括存储器设备和编程存储器设备的存储器单元的方法。 一种这样的方法可以包括在编程的第一次通过期间将第一偏置电压值应用于源极选择栅极以将存储器单元与源极隔离，在第一次处理期间将编程电压施加到存储器单元的页面的访问线 编程的通过，以及在源选择栅极施加第二偏置电压值以在第二次编程期间隔离存储器单元与源极。 公开了其它装置，系统和方法。

公开(公告)号：US11423976B2

公开(公告)日：2022-08-23

申请号：US16896750

申请日：2020-06-09

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08 ,  G11C16/20 ,  G11C16/26 ,  G11C7/20 ,  G11C16/04

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US12119051B2

公开(公告)日：2024-10-15

申请号：US17884861

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1015 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/227 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483 ,  G11C2207/2281

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US10685702B2

公开(公告)日：2020-06-16

申请号：US15688645

申请日：2017-08-28

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C16/24 ,  G11C7/10 ,  G11C7/22 ,  G11C7/08 ,  G11C16/20 ,  G11C16/26 ,  G11C7/20 ,  G11C16/04

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US10090053B2

公开(公告)日：2018-10-02

申请号：US15954282

申请日：2018-04-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US09972391B2

公开(公告)日：2018-05-15

申请号：US14971634

申请日：2015-12-16

Applicant: Micron Technology, Inc.

Inventor： Koji Sakui ,  Takehiro Hasegawa ,  Mark Helm

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3427 ,  G11C16/3459

Abstract: Various embodiments, disclosed herein, include apparatus and methods to read a logic level in a selected memory cell in a selected string of a memory by sensing the logic level in response to a read current flowing through the selected string to a data line. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US09330777B2

公开(公告)日：2016-05-03

申请号：US14632556

申请日：2015-02-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Mark Helm ,  Pranav Kalavade ,  Charan Srinivasan

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459

Abstract: Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method can include applying, during a first pass of programming, a first bias voltage value to a source select gate to isolate memory cells from a source, applying a programming voltage to an access line of a page of the memory cells during the first pass of programming, and applying a second bias voltage value to the source select gate to isolate the memory cells from the source during a second pass of programming. Further devices, systems, and methods are disclosed.