公开(公告)号：US10663513B2

公开(公告)日：2020-05-26

申请号：US16416242

申请日：2019-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kevin G. Werhane ,  Nathaniel J. Meier ,  Bin Liu

IPC: G01R31/307 ,  G01R31/30 ,  H03L7/081 ,  H03K5/133 ,  H01J37/26 ,  G01R31/28 ,  G01R31/26 ,  G01R31/50

Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

公开(公告)号：US20190271739A1

公开(公告)日：2019-09-05

申请号：US16416242

申请日：2019-05-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kevin G. Werhane ,  Nathaniel J. Meier ,  Bin Liu

IPC: G01R31/307 ,  H03K5/133 ,  G01R31/30 ,  H03L7/081 ,  H01J37/26

Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

公开(公告)号：US10330726B2

公开(公告)日：2019-06-25

申请号：US15626941

申请日：2017-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kevin G. Werhane ,  Nathaniel J. Meier ,  Bin Liu

IPC: G01R31/26 ,  G01R31/307 ,  G01R31/30 ,  H03L7/081 ,  H03K5/133 ,  H01J37/26

Abstract: Apparatuses including test segment circuits and methods for testing the same are disclosed. An example apparatus includes a plurality of segment lines configured to form a ring around a die and a plurality of test segment circuits, each test segment circuit coupled to at least two segment lines of the plurality of segment lines. Each test segment circuit is coupled to a portion of a first signal line, a portion of a second signal line, and a portion of a third signal line and each test segment circuit is configured to control an operation performed on at least one segment line of the plurality of segment lines.

公开(公告)号：US20240330081A1

公开(公告)日：2024-10-03

申请号：US18605006

申请日：2024-03-14

Applicant: Micron Technology, Inc.

Inventor： Chikara Kondo ,  Nathaniel J. Meier ,  Tomoki Hayashi ,  Roman A. Royer ,  Sean K. Moss ,  Stewart R. Watson

IPC: G06F9/54

CPC classification number: G06F9/542

Abstract: An apparatus including a selectable event reporter internal to a memory device and associated systems and methods are disclosed herein. In some embodiments, the selectable event reporter is dynamically configured to load user-defined event parameters. The selectable event reporter uses the user-defined event parameters to detect corresponding states in command and address signals provided by an external processor. The selectable event reporter communicates the detected events and/or other related observations to an external device.

公开(公告)号：US12086270B2

公开(公告)日：2024-09-10

申请号：US18166365

申请日：2023-02-08

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Markus H. Geiger ,  Nathaniel J. Meier

IPC: G06F11/00 ,  G06F21/55 ,  G06F21/57 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  G11C29/52

CPC classification number: G06F21/577 ,  G06F21/554 ,  G11C8/18 ,  G11C29/022 ,  G11C29/50004 ,  G11C29/52 ,  G06F2221/034 ,  G11C2029/5002

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

公开(公告)号：US11984148B2

公开(公告)日：2024-05-14

申请号：US17470883

申请日：2021-09-09

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C11/406 ,  G11C11/408

CPC classification number: G11C11/40611 ,  G11C11/4085 ,  G11C11/4087

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.

公开(公告)号：US11610622B2

公开(公告)日：2023-03-21

申请号：US17226975

申请日：2021-04-09

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Nathaniel J. Meier ,  Joo-Sang Lee

IPC: G11C11/00 ,  G11C11/406 ,  H01L25/065

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for staggering the timing of skipped refresh operations on a memory. Memory cells of memories may need to periodically perform refresh operations. In some instances, auto-refresh operations may be periodically skipped when charge retention characteristics of the memory cells of the memory exceed the auto-refresh frequency. To reduce peak current draw during refresh operations, the skipped refresh operations may be staggered across different portions of the memory. In one example, the skipped refresh operation may be staggered in time among memory dies of the memory to limit a number of memory dies that are performing an auto-refresh operation to a maximum number. In another example, the skipped refresh operation may be staggered in time among memory banks of a single memory array to limit a number of memory banks that are performing an auto-refresh operation to a maximum number.

公开(公告)号：US11520711B2

公开(公告)日：2022-12-06

申请号：US17338534

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Brenton P. Van Leeuwen ,  Nathaniel J. Meier

IPC: G06F12/14 ,  G06F12/00 ,  G11C17/16 ,  G06F21/78 ,  H04L9/08

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which security measures may be implemented to control access to a fuse array (or other secure features) of the memory devices based on a secure access key. In some cases, a customer may define and store a user-defined access key in the fuse array. In other cases, a manufacturer of the memory device may define a manufacturer-defined access key (e.g., an access key based on fuse identification (FID), a secret access key), where a host device coupled with the memory device may obtain the manufacturer-defined access key according to certain protocols. The memory device may compare an access key included in a command directed to the memory device with either the user-defined access key or the manufacturer-defined access key to determine whether to permit or prohibit execution of the command based on the comparison.

公开(公告)号：US20220148645A1

公开(公告)日：2022-05-12

申请号：US17091969

申请日：2020-11-06

Applicant: Micron Technology, Inc.

Inventor： Nathaniel J. Meier ,  James S. Rehmeyer ,  David R. Brown

IPC: G11C11/406 ,  G06F3/06

Abstract: Methods, apparatuses, and systems related to managing operations performed in response to refresh management (RFM) commands. A controller generates the RFM command for coordinating a refresh management operation targeted for implementation at an apparatus. The apparatus tracks refresh target set that includes refresh management target locations within the apparatus. According to the tracked refresh management target set, the apparatus selectively implements the targeted refresh management operation and/or a response operation in addition to or as a replacement for the targeted refresh management operation.

公开(公告)号：US11158364B2

公开(公告)日：2021-10-26

申请号：US16428625

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Daniel B. Penney ,  Jason M. Brown ,  Nathaniel J. Meier ,  Timothy B. Cowles ,  Jiyun Li

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/408

Abstract: The address of victim rows may be determined based on rows that are accessed in a memory. The victim addresses may be stored and associated with a count for every time a victim row is “victimized.” When the count for a victim row reaches a threshold, the victim row may be refreshed to preserve data stored in the row. After the victim row has been refreshed, the count may be reset. When a victim row is accessed, the count may also be reset. The counts may be adjusted for closer victim rows (e.g., +/−1) at a faster rate than counts for more distant victim rows (e.g., +/−2). This may cause closer victim rows to be refreshed at a higher rate than more distant victim rows.