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    Devices, systems and methods for electrostatic force enhanced semiconductor bonding
    12.
    发明授权
    Devices, systems and methods for electrostatic force enhanced semiconductor bonding 有权

    公开(公告)号：US10153190B2

    公开(公告)日：2018-12-11

    申请号：US14173489

    申请日：2014-02-05

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Ming Zhang

    IPC: H01L21/683 ,  H01L21/762

    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

    Methods of Forming Doped Regions in Semiconductor Substrates
    15.
    发明申请
    Methods of Forming Doped Regions in Semiconductor Substrates 有权
    在半导体衬底中形成掺杂区域的方法

    公开(公告)号：US20130072006A1

    公开(公告)日：2013-03-21

    申请号：US13674674

    申请日：2012-11-12

    Applicant: Micron Technology, Inc.

    Inventor： Lequn Jennifer Liu ,  Shu Qin ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/223

    CPC classification number: H01L21/2236 ,  H01L21/26506 ,  H01L21/2652 ,  H01L21/26526 ,  H01L29/66575

    Abstract: Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopant to a second depth within the substrate. In some embodiments the first dopant is p-type (such as boron) and the second dopant is neutral type (such as germanium). In some embodiments the second dopant is heavier than the first dopant.

    Abstract translation: 一些实施例包括在半导体衬底中形成一个或多个掺杂区域的方法。 可以使用等离子体掺杂来形成第一掺杂剂到衬底内的第一深度。 然后可以用第二掺杂剂冲击第一掺杂剂以将第一掺杂剂敲入衬底内的第二深度。 在一些实施方案中，第一掺杂剂是p型（例如硼），第二掺杂剂是中性型（例如锗）。 在一些实施方案中，第二掺杂剂比第一掺杂剂重。

    Plasma doping of gap fill materials
    16.
    发明授权
    Plasma doping of gap fill materials 有权

    公开(公告)号：US12040182B2

    公开(公告)日：2024-07-16

    申请号：US17971376

    申请日：2022-10-21

    Applicant: Micron Technology, Inc.

    Inventor： Santanu Sarkar ,  Jay Steven Brown ,  Shu Qin ,  Yongjun Jeff Hu ,  Farrell Martin Good

    IPC: H01L21/02 ,  H01L21/3105 ,  H10B63/00

    CPC classification number: H01L21/02282 ,  H01L21/02129 ,  H01L21/0234 ,  H01L21/31053 ,  H10B63/84

    Abstract: In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

    Integrated Assemblies and Methods of Forming Assemblies
    17.
    发明申请
    Integrated Assemblies and Methods of Forming Assemblies 有权

    公开(公告)号：US20210082703A1

    公开(公告)日：2021-03-18

    申请号：US16950115

    申请日：2020-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  Shu Qin

    IPC: H01L21/225 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/28

    Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

    Integrated assemblies containing germanium
    18.
    发明授权
    Integrated assemblies containing germanium 有权

    公开(公告)号：US10256098B2

    公开(公告)日：2019-04-09

    申请号：US14927217

    申请日：2015-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  Shu Qin

    IPC: H01L21/28 ,  H01L21/225 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
    19.
    发明申请
    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS 审中-公开

    公开(公告)号：US20190088867A9

    公开(公告)日：2019-03-21

    申请号：US15882666

    申请日：2018-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall

    Memory cells and methods of forming memory cells
    20.
    发明授权
    Memory cells and methods of forming memory cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US09496495B2

    公开(公告)日：2016-11-15

    申请号：US15176609

    申请日：2016-06-08

    Applicant: Micron Technology, Inc.

    Inventor： Martin Schubert ,  Shu Qin ,  Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy ,  Allen McTeer ,  Yongjun Jeff Hu

    IPC: H01L21/20 ,  H01L45/00

    CPC classification number: H01L45/1608 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/146 ,  H01L45/16

    Abstract: Some embodiments include a memory cell having a first electrode, and an intermediate material over and directly against the first electrode. The intermediate material includes stabilizing species corresponding to one or both of carbon and boron. The memory cell also has a switching material over and directly against the intermediate material, an ion reservoir material over the switching material, and a second electrode over the ion reservoir material. Some embodiments include methods of forming memory cells.

    Abstract translation: 一些实施例包括具有第一电极的存储器单元，以及在第一电极之上并直接抵靠第一电极的中间材料。 中间材料包括对应于碳和硼之一或两者的稳定物质。 存储单元还具有超过并直接抵靠中间材料的开关材料，开关材料上方的离子储存器材料以及离子储存器材料上的第二电极。 一些实施例包括形成存储器单元的方法。

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