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    DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING
    1.
    发明申请
    DEVICES, SYSTEMS AND METHODS FOR ELECTROSTATIC FORCE ENHANCED SEMICONDUCTOR BONDING 有权

    公开(公告)号：US20210366758A1

    公开(公告)日：2021-11-25

    申请号：US17395389

    申请日：2021-08-05

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Ming Zhang

    IPC: H01L21/683 ,  H01L21/762

    Abstract: Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for enhancing wafer bonding includes positioning a substrate assembly on a unipolar electrostatic chuck in direct contact with an electrode, electrically coupling a conductor to a second substrate positioned on top of the first substrate, and applying a voltage to the electrode, thereby creating a potential differential between the first substrate and the second substrate that generates an electrostatic force between the first and second substrates.

    Phase change memory stack with treated sidewalls
    2.
    发明授权
    Phase change memory stack with treated sidewalls 有权

    公开(公告)号：US10224479B2

    公开(公告)日：2019-03-05

    申请号：US15882666

    申请日：2018-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

    Semiconductor Devices, and Methods of Forming Semiconductor Devices
    6.
    发明申请
    Semiconductor Devices, and Methods of Forming Semiconductor Devices 有权
    半导体器件和半导体器件的形成方法

    公开(公告)号：US20160211324A1

    公开(公告)日：2016-07-21

    申请号：US14597766

    申请日：2015-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Shu Qin ,  Yongjun Jeff Hu ,  Allen McTeer

    IPC: H01L29/08 ,  H01L21/223 ,  H01L27/092 ,  H01L29/45

    CPC classification number: H01L29/0847 ,  H01L21/2236 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/823418 ,  H01L27/092 ,  H01L29/456 ,  H01L29/665

    Abstract: Some embodiments include a device having an n-type diffusion region, and having a boron-doped region within the n-type diffusion region. The boron-doped region extends no deeper than about 10 nanometers from an upper surface of the n-type diffusion region. Some embodiments include a method in which first boron-enhanced regions are formed within upper portions of n-type source/drain regions of an NMOS (n-type metal-oxide-semiconductor) device and second boron-enhanced regions are simultaneously formed within upper portions of p-type source/drain regions of a PMOS (p-type metal-oxide-semiconductor) device. The first and second boron-enhanced regions extend to depths of less than or equal to about 10 nanometers.

    Abstract translation: 一些实施例包括具有n型扩散区的器件，并且在n型扩散区内具有硼掺杂区。 硼掺杂区从n型扩散区的上表面延伸不超过约10纳米。 一些实施例包括其中在NMOS（n型金属氧化物 - 半导体）器件的n型源极/漏极区的上部形成第一硼增强区的方法，并且第二硼增强区同时形成在上部 PMOS（p型金属氧化物半导体）器件的p型源/漏区的部分。 第一和第二硼增强区域延伸到小于或等于约10纳米的深度。

    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
    7.
    发明申请
    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS 有权
    相位变化的存储堆栈与处理的SIDEWALLS

    公开(公告)号：US20150318468A1

    公开(公告)日：2015-11-05

    申请号：US14266415

    申请日：2014-04-30

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/06 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/165 ,  H01L45/1675

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

    Abstract translation: 已经公开了用于制造存储器件的存储器件和方法。 一种这样的方法包括从多个元件形成存储器堆叠。 在存储器堆叠的至少一个侧壁上形成粘附物质，其中粘附物质具有梯度结构，其导致粘附物质与存储器堆叠的元件混合以终止元件的不满足的原子键。 梯度结构还包括在至少一个侧壁的外表面上的粘附物质的膜。 将电介质材料注入到粘附物质的膜中以形成侧壁衬里。

    Methods of forming assemblies having heavily doped regions
    9.
    发明授权
    Methods of forming assemblies having heavily doped regions 有权

    公开(公告)号：US11658033B2

    公开(公告)日：2023-05-23

    申请号：US16950115

    申请日：2020-11-17

    Applicant: Micron Technology, Inc.

    Inventor： Yushi Hu ,  Shu Qin

    IPC: H01L21/225 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11582

    CPC classification number: H01L21/2253 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/40114 ,  H01L29/40117

    Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS
    10.
    发明申请
    PHASE CHANGE MEMORY STACK WITH TREATED SIDEWALLS 审中-公开

    公开(公告)号：US20190355902A1

    公开(公告)日：2019-11-21

    申请号：US16266777

    申请日：2019-02-04

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

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