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    POLYMER COATED SEMICONDUCTOR DEVICES AND HYBRID BONDING TO FORM SEMICONDUCTOR ASSEMBLIES
    13.
    发明申请
    POLYMER COATED SEMICONDUCTOR DEVICES AND HYBRID BONDING TO FORM SEMICONDUCTOR ASSEMBLIES 有权

    公开(公告)号：US20230065248A1

    公开(公告)日：2023-03-02

    申请号：US17820199

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Eiichi Nakano ,  Ying Ta Chiu

    IPC: H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

    Abstract: A semiconductor device assembly including a first semiconductor device having a front side and a back side opposite of the front side, metal interconnects formed on the back side, and a polymer material deposited over the first semiconductor device to encapsulate the sidewalls, back side, and metal interconnects. The first semiconductor device is planarized to expose the upper surface of the metal interconnects. The assembly further includes a second semiconductor device having a top side and a bottom side opposite of the top side, a polymer material deposited over the second semiconductor device to encapsulate the sidewalls and bottom side. The second semiconductor device is stacked over the first device and hybrid bonded together such that each metal interconnect on the first semiconductor device back side aligns with and electrically couples to a corresponding metal interconnect on the second semiconductor device bottom side.

    CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS
    14.
    发明申请
    CONDUCTIVE BUFFER LAYERS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED SYSTEMS AND METHODS 有权

    公开(公告)号：US20230063954A1

    公开(公告)日：2023-03-02

    申请号：US17411229

    申请日：2021-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou

    IPC: H01L23/00

    Abstract: Conductive buffer layers for semiconductor die assemblies, and associated systems and methods are disclosed. In an embodiment, a semiconductor die assembly includes first and second semiconductor dies directly bonded to each other. The first semiconductor die includes a first copper pad and the second semiconductor die includes a second copper pad. The first and second copper pads form an interconnect between the first and second semiconductor dies, and the interconnect includes a conductive buffer material between the first and second copper pads, where the conductive buffer material includes aggregates of conductive particles. In some embodiments, the first and second copper pads are not conjoined but electrically connected to each other through the conductive buffer material. In some embodiments, the conductive buffer material is porous such that the aggregates of conductive particles can be compressed together in response to the pressure applied to the conductive buffer layer.

    Methods and systems for manufacturing semiconductor devices
    15.
    发明授权
    Methods and systems for manufacturing semiconductor devices 有权

    公开(公告)号：US11410963B2

    公开(公告)日：2022-08-09

    申请号：US17099655

    申请日：2020-11-16

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

    IPC: H01L21/00 ,  H01L23/00 ,  H01L23/48

    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

    METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES
    16.
    发明申请
    METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200212000A1

    公开(公告)日：2020-07-02

    申请号：US16236257

    申请日：2018-12-28

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street ,  Benjamin L. McClain ,  Mark E. Tuttle

    IPC: H01L23/00 ,  H01L23/48

    Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

    Semiconductor device with a layered protection mechanism and associated systems, devices, and methods
    18.
    发明授权
    Semiconductor device with a layered protection mechanism and associated systems, devices, and methods 有权

    公开(公告)号：US10381329B1

    公开(公告)日：2019-08-13

    申请号：US15878755

    申请日：2018-01-24

    Applicant: Micron Technology, Inc.

    Inventor： Wei Zhou ,  Bret K. Street

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495 ,  H01L23/48 ,  H01L25/00 ,  H01L23/64

    Abstract: A semiconductor device includes a first die; a second die attached over the first die; a first metal enclosure and a second metal enclosure both directly contacting and vertically extending between the first die and the second die, wherein the first metal enclosure peripherally encircles a set of one or more internal interconnects and the second metal enclosure peripherally encircles the first metal enclosure without directly contacting the first metal enclosure; a first enclosure connector electrically connecting the first metal enclosure to a first voltage level; a second enclosure connector electrically connecting the second metal enclosure to a second voltage level; and wherein the first metal enclosure, the second metal enclosure, the first enclosure connector, and the second enclosure connector are configured to provide an enclosure capacitance.

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