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公开(公告)号：US09791642B2
公开(公告)日：2017-10-17
申请号：US15436934
申请日：2017-02-20
CPC分类号： G02B6/4228 , G02B6/1221 , G02B6/4231 , G02B6/4257 , G02B2006/12147 , H01L21/6838 , H01L2224/08135 , H01L2224/08145 , H01L2224/08147 , H01L2224/08148 , H01L2224/08221 , H01L2224/08237 , H01L2224/08238 , H01L2224/81141 , H01L2224/81898
摘要： A chip packaging includes a first part comprising a support; and a core polymer layer transversally structured so as to exhibit distinct residual portions comprising: first waveguide cores each having a first height and disposed within said inner region; and one or more first alignment structures disposed within said outer region. A second part of the packaging comprises: second waveguide cores, each having a same second height; and one or more second alignment structures complementarily shaped with respect to the one or more first alignment structures, and wherein, the first part structured such that said inner region is recessed with respect to the outer region, to enable: the second waveguide cores to contact the first waveguide cores; and the one or more second alignment structures to respectively receive, at least partly, the one or more first alignment structures. The invention is further directed to related passive alignment methods.
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公开(公告)号：US09671577B2
公开(公告)日：2017-06-06
申请号：US14848585
申请日：2015-09-09
IPC分类号： G02B6/26 , G02B6/42 , H01L21/683 , G02B6/12
CPC分类号： G02B6/4228 , G02B6/1221 , G02B6/4231 , G02B6/4257 , G02B2006/12147 , H01L21/6838 , H01L2224/08135 , H01L2224/08145 , H01L2224/08147 , H01L2224/08148 , H01L2224/08221 , H01L2224/08237 , H01L2224/08238 , H01L2224/81141 , H01L2224/81898
摘要： A chip packaging includes a first part comprising a support; and a core polymer layer transversally structured so as to exhibit distinct residual portions comprising: first waveguide cores each having a first height and disposed within said inner region; and one or more first alignment structures disposed within said outer region. A second part of the packaging comprises: second waveguide cores, each having a same second height; and one or more second alignment structures complementarily shaped with respect to the one or more first alignment structures, and wherein, the first part structured such that said inner region is recessed with respect to the outer region, to enable: the second waveguide cores to contact the first waveguide cores; and the one or more second alignment structures to respectively receive, at least partly, the one or more first alignment structures. The invention is further directed to related passive alignment methods.
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公开(公告)号：US09589891B2
公开(公告)日：2017-03-07
申请号：US14946517
申请日：2015-11-19
发明人： Hsien-Wei Chen , Jie Chen , Ying-Ju Chen
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/528 , H01L21/768 , H01L23/31 , H01L23/00 , H01L23/525
CPC分类号： H01L24/02 , H01L21/76895 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L23/525 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05548 , H01L2224/05567 , H01L2224/05583 , H01L2224/05644 , H01L2224/08145 , H01L2224/08221 , H01L2224/11334 , H01L2224/11849 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/3512 , H01L2924/00014 , H01L2924/0105 , H01L2924/00012 , H01L2924/01047
摘要： Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.
摘要翻译： 公开了用于半导体器件的封装装置及其制造方法。 在一些实施例中，包装装置包括设置在衬底上的接触垫，以及设置在衬底上的钝化层和/或聚合物层和接触垫的一部分。 后钝化互连（PPI）线设置在钝化层上并且耦合到接触焊盘的暴露部分。 PPI垫设置在钝化层上。 过渡元件设置在钝化层上并且耦合在PPI线和PPI衬垫之间。 过渡元件包括宽度大于PPI线的线。
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公开(公告)号：US20240266255A1
公开(公告)日：2024-08-08
申请号：US18398984
申请日：2023-12-28
IPC分类号： H01L23/473 , H01L21/48 , H01L23/00
CPC分类号： H01L23/4735 , H01L21/4871 , H01L24/08 , H01L24/80 , H01L2224/08221 , H01L2224/80896
摘要： A cooling structure having a first side and a second side opposite the first side can be formed through a method comprising, forming an inlet and an outlet in a first substrate, forming at least one channel on the second side of the first substrate, wherein the at least one channel is in fluid communication with the inlet and outlet, forming a plurality of nozzles on the first side of a second substrate, and forming a plurality of channels on the second side of the second substrate opposite the first side of the second substrate. The plurality of channels is aligned with the plurality of nozzles, and the second side of the first substrate is bonded to the first side of the second substrate.
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5.发明授权公开(公告)号：US11670625B2
公开(公告)日：2023-06-06
申请号：US16979592
申请日：2019-01-30
发明人： Masahiko Yukawa
IPC分类号： H01L25/16 , H01L27/146 , H01L23/00
CPC分类号： H01L25/167 , H01L24/08 , H01L24/32 , H01L27/1469 , H01L27/14634 , H01L27/14636 , H01L2224/08145 , H01L2224/08221 , H01L2224/32145
摘要： Provided is a solid-state imaging unit that includes a stacked structure including a sensor substrate and a circuit board. The sensor board has an effective pixel region where an imaging device is disposed. The imaging device includes a plurality of pixels and is configured to receive external light in each of the pixels to generate a pixel signal. The circuit board includes a chip including a first portion and a second portion that are integrated with each other. The first portion includes a signal processing circuit that performs signal processing of the pixel signal. The second portion is disposed at a position different from a position of the first portion in an in-plane direction. Here, both the first portion and the second portion are disposed to overlap the effective pixel region in a stacking direction of the sensor board and the circuit board.
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公开(公告)号：US20170179051A1
公开(公告)日：2017-06-22
申请号：US15449727
申请日：2017-03-03
发明人： Jie Chen , Hsien-Wei Chen , Ying-Ju Chen
IPC分类号： H01L23/00
CPC分类号： H01L24/02 , H01L21/76895 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L23/525 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/02311 , H01L2224/02331 , H01L2224/0235 , H01L2224/0239 , H01L2224/0401 , H01L2224/05008 , H01L2224/05009 , H01L2224/05022 , H01L2224/05124 , H01L2224/05155 , H01L2224/05164 , H01L2224/05548 , H01L2224/05567 , H01L2224/05583 , H01L2224/05644 , H01L2224/08145 , H01L2224/08221 , H01L2224/11334 , H01L2224/11849 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13024 , H01L2224/13111 , H01L2224/13116 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01079 , H01L2924/3512 , H01L2924/00014 , H01L2924/0105 , H01L2924/00012 , H01L2924/01047
摘要： Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.
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公开(公告)号：US20170160472A1
公开(公告)日：2017-06-08
申请号：US15436934
申请日：2017-02-20
CPC分类号： G02B6/4228 , G02B6/1221 , G02B6/4231 , G02B6/4257 , G02B2006/12147 , H01L21/6838 , H01L2224/08135 , H01L2224/08145 , H01L2224/08147 , H01L2224/08148 , H01L2224/08221 , H01L2224/08237 , H01L2224/08238 , H01L2224/81141 , H01L2224/81898
摘要： A chip packaging includes a first part comprising a support; and a core polymer layer transversally structured so as to exhibit distinct residual portions comprising: first waveguide cores each having a first height and disposed within said inner region; and one or more first alignment structures disposed within said outer region. A second part of the packaging comprises: second waveguide cores, each having a same second height; and one or more second alignment structures complementarily shaped with respect to the one or more first alignment structures, and wherein, the first part structured such that said inner region is recessed with respect to the outer region, to enable: the second waveguide cores to contact the first waveguide cores; and the one or more second alignment structures to respectively receive, at least partly, the one or more first alignment structures. The invention is further directed to related passive alignment methods.
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公开(公告)号：US20240304580A1
公开(公告)日：2024-09-12
申请号：US18663124
申请日：2024-05-14
发明人： WEN-CHUAN TAI , FAN HU , HSIANG-FU CHEN , LI-CHUN PENG
CPC分类号： H01L24/08 , H01L21/50 , H01L23/10 , H01L24/09 , H01L24/80 , H01L2224/0801 , H01L2224/08053 , H01L2224/08059 , H01L2224/08221 , H01L2224/0903 , H01L2224/09055 , H01L2224/80203 , H01L2224/80805 , H01L2224/8083 , H01L2224/80895 , H01L2924/1611 , H01L2924/1616 , H01L2924/16235 , H01L2924/1631 , H01L2924/16315 , H01L2924/1632
摘要： A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.
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公开(公告)号：US12015001B2
公开(公告)日：2024-06-18
申请号：US17695815
申请日：2022-03-15
发明人： Wen-Chuan Tai , Fan Hu , Hsiang-Fu Chen , Li-Chun Peng
CPC分类号： H01L24/08 , H01L21/50 , H01L23/10 , H01L24/09 , H01L24/80 , H01L2224/0801 , H01L2224/08053 , H01L2224/08059 , H01L2224/08221 , H01L2224/0903 , H01L2224/09055 , H01L2224/80203 , H01L2224/80805 , H01L2224/8083 , H01L2224/80895 , H01L2924/1611 , H01L2924/1616 , H01L2924/16235 , H01L2924/1631 , H01L2924/16315 , H01L2924/1632
摘要： A bonding method and a bonding structure are provided. A device substrate is provided including a plurality of semiconductor devices, wherein each of the semiconductor devices includes a first bonding layer. A cap substrate is provided including a plurality of cap structures, wherein each of the cap structures includes a second bonding layer, the second bonding layer having a planar surface and a first protrusion protruding from the planar surface. The device substrate is bonded to the cap substrate by engaging the first protrusion of the second bonding layer of each of the cap structures with the corresponding first bonding layer of each of the semiconductor devices in the device substrate.
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公开(公告)号：US20240120315A1
公开(公告)日：2024-04-11
申请号：US18169579
申请日：2023-02-15
发明人： Ming-Fa Chen , Tze-Chiang Huang , Yun-Han Lee , Lee-Chung Lu
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/538 , H01L25/00 , H01L25/18 , H10B80/00
CPC分类号： H01L25/0652 , H01L23/3185 , H01L23/481 , H01L23/538 , H01L23/5384 , H01L24/05 , H01L24/06 , H01L24/08 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06181 , H01L2224/08147 , H01L2224/08221 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13164
摘要： A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.
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