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    APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICE
    12.
    发明公开
    APPARATUSES AND METHODS INCLUDING DICE LATCHES IN A SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230343376A1

    公开(公告)日：2023-10-26

    申请号：US18335385

    申请日：2023-06-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Yoshiro Riho ,  Hiroshi Akamatsu ,  Jian Long ,  Kevin G. Werhane ,  Liang Liu ,  Yoshinori Fujiwara

    IPC: G11C7/10

    CPC classification number: G11C7/1087

    Abstract: According to one or more embodiments, an apparatus comprising a plurality of dice latches, dice latch control logic, and a plurality of data input logic is provided. The dice latches are coupled in parallel and latch respective data. The dice latch control logic receives a load control signal and a reset control signal, provides a reset signal and further provides first and second load signals to the dice latches. The reset signal is based on the reset control signal. The first and second load signals are based on the load control signal and the reset control signal. The data input logic each are coupled to a respective one of the dice latches. Each of the data input logic receives a precharge control signal and respective input data and further provides data and complementary data to the respective one of the dice latches.

    Memory devices with multiple sets of latencies and methods for operating the same
    14.
    发明授权
    Memory devices with multiple sets of latencies and methods for operating the same 有权

    公开(公告)号：US11150821B2

    公开(公告)日：2021-10-19

    申请号：US16543467

    申请日：2019-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

    IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F13/16

    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

    MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPERATING THE SAME
    18.
    发明申请
    MEMORY DEVICES WITH MULTIPLE SETS OF LATENCIES AND METHODS FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20190129637A1

    公开(公告)日：2019-05-02

    申请号：US16048078

    申请日：2018-07-27

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans ,  Yoshiro Riho ,  Shunichi Saito ,  Osamu Nagashima

    IPC: G06F3/06

    Abstract: Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied.

    PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY
    19.
    发明申请
    PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY 有权
    动态随机访问存储器的部分访问模式

    公开(公告)号：US20150146494A1

    公开(公告)日：2015-05-28

    申请号：US14285279

    申请日：2014-05-22

    Applicant: Micron Technology, Inc.

    Inventor： Yoshiro Riho

    IPC: G11C11/406 ,  G11C5/14

    CPC classification number: G11C11/40615 ,  G11C11/40622

    Abstract: Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2N cells for both normal and self refresh operation modes.

    Abstract translation: 一些实施例提供了通过有效地延长存储器单元保留时间来减少刷新功率消耗的方法。 从1个单元/位转换为2N个单元/位减少了存储单元之间的保留时间的变化。 可以从DRAM阵列电路的结构非常简单地实现转换，并且将干扰和功耗的频率降低两个数量级。 基于该转换方法，一些实施例提供了部分访问模式，以便在不需要全存储器容量时动态地降低功耗。 一位数据可以存储在1个单元中用于正常操作模式，并且存储在2N个单元中用于第一部分访问模式的自刷新操作模式，而一个位数据可以存储在2N个单元中用于正常和自刷新操作模式 。

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