METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY
    18.
    发明申请
    METHOD OF ENHANCING LITHOGRAPHY CAPABILITIES DURING GATE FORMATION IN SEMICONDUCTORS HAVING A PRONOUNCED SURFACE TOPOGRAPHY 有权
    在具有预定表面形貌的半导体中增加栅格形成过程中的刻蚀能力的方法

    公开(公告)号:US20080026552A1

    公开(公告)日:2008-01-31

    申请号:US11773631

    申请日:2007-07-05

    IPC分类号: H01L21/4763

    CPC分类号: H01L21/28123 H01L29/66772

    摘要: In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

    摘要翻译: 在用于在半导体岛上形成晶体管的台面隔离结构中,执行附加的平面化步骤以增强栅极图案化工艺的均匀性。 在一些说明性实施例中,当栅电极材料形成在未填充的隔离沟槽上方时,栅电极材料可以例如基于CMP平坦化,以补偿高度不均匀的表面形貌。 因此,由于关键栅极图案化工艺的增强,台面隔离策略的显着优点可能与高度的可扩展性相结合。