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19 条记录 (耗时 0.035 秒)

    Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices
    5.
    发明授权
    Buried etch stop layer in trench isolation structures for superior surface planarity in densely packed semiconductor devices 有权
    在密集封装的半导体器件中，在沟槽隔离结构中埋设蚀刻停止层以获得出色的表面平面度

    公开(公告)号：US08334573B2

    公开(公告)日：2012-12-18

    申请号：US12858727

    申请日：2010-08-18

    申请人： Maciej Wiatr ,  Markus Forsberg ,  Stephan Kronholz ,  Roman Boschke

    发明人： Maciej Wiatr ,  Markus Forsberg ,  Stephan Kronholz ,  Roman Boschke

    IPC分类号： H01L27/088

    CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： Material erosion of trench isolation structures in advanced semiconductor devices may be reduced by incorporating an appropriate mask layer stack in an early manufacturing stage. For example, a silicon nitride material may be incorporated as a buried etch stop layer prior to a sequence for patterning active regions and forming a strain-inducing semiconductor alloy therein, wherein, in particular, the corresponding cleaning process prior to the selective epitaxial growth process has been identified as a major source for causing deposition-related irregularities upon depositing the interlayer dielectric material.

    摘要翻译： 先进的半导体器件中的沟槽隔离结构的材料侵蚀可以通过在早期制造阶段中合并适当的掩模层堆叠来减少。 例如，氮化硅材料可以在用于图案化有源区域并在其中形成应变诱导半导体合金的序列之前作为掩埋蚀刻停止层引入，其中特别地，在选择性外延生长工艺之前的相应的清洁工艺 已经被确定为在沉积层间介电材料时引起沉积相关不规则的主要来源。

    Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials
    8.
    发明授权
    Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materials 有权
    通过使用基于硅/锗材料的PN结，在半导体器件中的温度监测

    公开(公告)号：US08796807B2

    公开(公告)日：2014-08-05

    申请号：US13251532

    申请日：2011-10-03

    申请人： Rolf Stephan ,  Markus Forsberg ,  Gert Burbach ,  Anthony Mowry

    发明人： Rolf Stephan ,  Markus Forsberg ,  Gert Burbach ,  Anthony Mowry

    IPC分类号： H01L31/058

    CPC分类号： H01L27/0629 ,  H01L21/823807 ,  H01L27/1203

    摘要： By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon/germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

    摘要翻译： 通过将锗材料结合到热敏二极管结构中，其灵敏度可以显着增加。 在一些说明性实施例中，可以与用于将硅/锗材料并入复杂半导体器件的P沟道晶体管的工艺流程具有高兼容性来执行用于并入锗材料的工艺。 因此，可以降低模具面积消耗来提高温度控制效率。

    Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography
    9.
    发明授权
    Method of enhancing lithography capabilities during gate formation in semiconductors having a pronounced surface topography 有权
    在具有明显的表面形貌的半导体中增强栅极形成期间光刻能力的方法

    公开(公告)号：US08101512B2

    公开(公告)日：2012-01-24

    申请号：US11773631

    申请日：2007-07-05

    申请人： Martin Gerhardt ,  Martin Trentzsch ,  Markus Forsberg ,  Manfred Horstmann

    发明人： Martin Gerhardt ,  Martin Trentzsch ,  Markus Forsberg ,  Manfred Horstmann

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28123 ,  H01L29/66772

    摘要： In a mesa isolation configuration for forming a transistor on a semiconductor island, an additional planarization step is performed to enhance the uniformity of the gate patterning process. In some illustrative embodiments, the gate electrode material may be planarized, for instance, on the basis of CMP, to compensate for the highly non-uniform surface topography, when the gate electrode material is formed above the non-filled isolation trenches. Consequently, significant advantages of the mesa isolation strategy may be combined with a high degree of scalability due to the enhancement of the critical gate patterning process.

    摘要翻译： 在用于在半导体岛上形成晶体管的台面隔离结构中，执行附加的平面化步骤以增强栅极图案化工艺的均匀性。 在一些说明性实施例中，当栅电极材料形成在未填充的隔离沟槽上方时，栅电极材料可以例如基于CMP平坦化，以补偿高度不均匀的表面形貌。 因此，由于关键栅极图案化工艺的增强，台面隔离策略的显着优点可能与高度可扩展性相结合。

    SOI DEVICE HAVING A SUBSTRATE DIODE FORMED BY REDUCED IMPLANTATION ENERGY
    10.
    发明申请
    SOI DEVICE HAVING A SUBSTRATE DIODE FORMED BY REDUCED IMPLANTATION ENERGY 有权
    具有通过减少植入能量形成的基底二极管的SOI器件

    公开(公告)号：US20090111223A1

    公开(公告)日：2009-04-30

    申请号：US12113271

    申请日：2008-05-01

    申请人： Maciej Wiatr ,  Markus Forsberg ,  Roman Boschke

    发明人： Maciej Wiatr ,  Markus Forsberg ,  Roman Boschke

    IPC分类号： H01L21/336

    CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7843

    摘要： By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, thereby increasing process uniformity and significantly reducing cycle time of the implantation process. Thus, enhanced reliability and stability of the substrate diode may be accomplished while also providing a high degree of compatibility with conventional manufacturing techniques.

    摘要翻译： 通过在SOI器件中形成隔离结构的沟槽开口期间去除材料，用于限定衬底二极管的阱区的后续注入工艺可以在适度低的注入能量的基础上进行，从而增加工艺均匀性并显着减少循环 植入过程的时间。 因此，可以实现衬底二极管的增强的可靠性和稳定性，同时还提供与常规制造技术的高度兼容性。