-
11.发明授权Single-chip pipeline processor for fetching/flushing instruction/data caches in response to first/second hit/mishit signal respectively detected in corresponding to their logical addresses 失效单芯片流水线处理器，用于根据其逻辑地址分别检测到的第一/第二命中/虚拟信号来提取/刷新指令/数据高速缓存
公开(公告)号：US5206945A
公开(公告)日：1993-04-27
申请号：US606804
申请日：1990-10-31
CPC分类号： G06F9/3802 , G06F12/0848 , G06F12/0891 , G06F9/30047 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有存储从主存储器读出的指令的第一关联存储器，以及指令控制单元，当指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。
-
公开(公告)号：US5148532A
公开(公告)日：1992-09-15
申请号：US611484
申请日：1990-11-07
IPC分类号： G06F9/26
CPC分类号： G06F9/264
摘要： In a pipeline processing microprocessor, an instruction fetch unit is keyed to the formation or nonformation of a conditional branch micro-instruction result to determine the subsequent macro-instruction to be fetched from an external memory or cache. A macro-instruction is first decoded in an instruction decoder to generate micro-addresses which address is a micro-ROM. The first micro-instruction retrieved from the micro-ROM contains information for executing a conditional discrimination, a signal requesting branch ready, and a subsequent micro-address for the actual execution of the branch request in accordance with the result of the conditional discrimination. When the branch condition is satisfied, a micro-address generating circuit feeds the subsequent micro-instruction to a micro-ROM address decoder and the least significant bit of the subsequent micro-address to a micro-address analyzing circuit. The branch ready information of the first micro-instruction is also fed to the micro-address analyzing circuit to prefetch a target branch macro-instruction from an associated memory before the micro-ROM outputs the micro-instruction, corresponding to the subsequent micro-address, to the instruction execution unit, in effect bypassing the delay associated with micro-ROM decoding.
-
13.发明授权Data processor with on-chip logical addressing and off-chip physical addressing 失效具有片上逻辑寻址和片外物理寻址的数据处理器
公开(公告)号：US5129075A
公开(公告)日：1992-07-07
申请号：US596751
申请日：1990-10-12
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory, and the instruction control unit also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory. The instruction controller provides the instruction to be executed as an output. The data processor further includes an instruction execution unit having a second associative memory storing operand data read out from the main memory, and an instruction execution unit that executes the instruction. The instruction execution unit uses operand data read out from the second associative memory when the operand data is present in the second associative memory and operand data from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器，并且指令控制单元还包括指令控制器，其从第一 当指令存在于第一关联存储器中时，并且当指令不存在于第一关联存储器中时，与主存储器相关联的存储器。 指令控制器提供要作为输出执行的指令。 数据处理器还包括具有存储从主存储器读出的操作数数据的第二关联存储器的指令执行单元和执行该指令的指令执行单元。 当操作数数据存在于第二关联存储器中时，指令执行单元使用从第二关联存储器读出的操作数数据，当操作数数据不存在于第二关联存储器中时，来自主存储器的操作数数据。
-
公开(公告)号：US4845614A
公开(公告)日：1989-07-04
申请号：US83169
申请日：1987-08-10
CPC分类号： G06F11/141
摘要： A microprocessor and a peripheral equipment communicate data through a bus. If an error occurs during communication, the microprocessor starts the next bus cycle and commands retry of the data communication. If a predetermined number of times of retry fail, and if an address signal corresponds to an unmounted area of an address space, wherein the unmounted area is an area of the address space not occupied by peripheral equipment including an I/O device, the microprocessor inhibits the retry.
摘要翻译： 微处理器和外围设备通过总线传送数据。 如果在通信过程中发生错误，则微处理器启动下一个总线周期并命令重试数据通信。 如果预定次数的重试失败，并且如果地址信号对应于地址空间的未安装区域，其中未安装区域是未被包括I / O设备的外围设备占用的地址空间的区域，微处理器 禁止重试。
-
公开(公告)号：US06272596B1
公开(公告)日：2001-08-07
申请号：US09396414
申请日：1999-09-15
IPC分类号： G06F1202
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令的输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
-
16.发明授权RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register 失效RISC系统能够通过旁路寄存器在一个时钟周期内同时执行数据互锁位移和算术/逻辑指令
公开(公告)号：US5269007A
公开(公告)日：1993-12-07
申请号：US609408
申请日：1990-11-05
申请人： Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Hanawa , Tadahiko Nishimukai
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/30167 , G06F9/3822 , G06F9/3824
摘要： First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file, an arithmetic and logic unit, and a shifter. A first comparator compares a destination field of the first instruction with a first source field of the second instruction. The shifter produces an output in association with immediate data of the first instruction, the output being ordinarily stored in a register file. However, when both inputs of the comparator are identical to each other, the output from the shifter is supplied to an input of the arithmetic and logic unit via a bypass signal transmission path.
-
公开(公告)号：US5974533A
公开(公告)日：1999-10-26
申请号：US113550
申请日：1998-07-10
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的输出指令。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
-
18.发明授权
公开(公告)号：US5349672A
公开(公告)日：1994-09-20
申请号：US503128
申请日：1990-04-03
CPC分类号： G06F9/3802 , G06F12/0848 , G06F12/0891 , G06F9/3824
摘要： A data processor is used with a main memory that stores operand data and instructions. The data processor itself includes two cache memories, one of which stores logical instruction addresses and corresponding instructions while the other stores logical operand addresses and corresponding operand data. A selector chooses whether a logical operand address or logical instruction address should access the respective cache memory or the main memory to obtain an instruction or operand data. Furthermore, the processor includes the capability of invalidating all of the data in either the instruction cache memory or operand cache memory based on a software instruction signal received at a purge unit.
摘要翻译： 数据处理器与存储操作数数据和指令的主存储器一起使用。 数据处理器本身包括两个高速缓冲存储器，其中之一存储逻辑指令地址和对应的指令，而另一个存储逻辑操作数地址和相应的操作数数据。 选择器选择逻辑操作数地址或逻辑指令地址是否应该访问相应的高速缓冲存储器或主存储器以获得指令或操作数据。 此外，处理器包括基于在清除单元处接收的软件指令信号使指令高速缓冲存储器或操作数高速缓冲存储器中的所有数据无效的能力。
-
19.发明授权Single-chip-cache-buffer for selectively writing write-back and exclusively writing data-block portions to main-memory based upon indication of bits and bit-strings respectively 失效单片缓存缓冲器，用于基于位和位串的指示，有选择地写入回写和独占地将数据块部分写入主存储器
公开(公告)号：US5202969A
公开(公告)日：1993-04-13
申请号：US871906
申请日：1992-04-21
申请人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
发明人： Katsuyuki Sato , Tadahiko Nishimukai , Kunio Uchiyama , Hirokazu Aoki , Susumu Hatano , Kanji Oishi , Hiroshi Fukuta , Takashi Kikuchi , Yasuhiko Saigou
IPC分类号： G06F12/08 , G11C11/4096
CPC分类号： G06F12/0804 , G11C11/4096
摘要： In a cache memory setup, a buffer register is provided to accommodate the data read from a data memory. Between the buffer register and the data memory is connected a selector. This selector selectively transfers to the buffer register part of the data read from the data memory. The remaining part of the data is replaced with appropriate data for transfer to the buffer register. This arrangement provides the cache memory with a partial-write function.
摘要翻译： 在缓存存储器设置中，提供缓冲寄存器以容纳从数据存储器读取的数据。 在缓冲寄存器和数据存储器之间连接一个选择器。 该选择器选择性地将从数据存储器读取的数据传送到缓冲寄存器部分。 数据的剩余部分被替换为适当的数据以传送到缓冲寄存器。 这种布置为高速缓冲存储器提供部分写入功能。
-
20.发明授权Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction 失效数据处理系统，其基于指令的位信息选择性地绕过高速缓冲存储器取得信息
公开(公告)号：US4937738A
公开(公告)日：1990-06-26
申请号：US768572
申请日：1985-08-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0888
摘要： A cache memory contained in a processor features a high efficiency in spite of its small capacity.In the cache memory control circuit, it is detected whether the access operation of the processor is directed to a particular region of the memory, and when the data is to be read out from, or is to be written onto, the particular region, the data is copied onto the cache memory and when the data is to be read out from other regions, operation of the memory is executed immediately without waiting for the reference of cache memory.By assigning the particular region for the data that is to be used repeatedly, it is possible to provide a cache memory having good efficiency in spite of its small capacity. A representative example of such data is the data in a stack.
摘要翻译： 包含在处理器中的高速缓冲存储器具有高效率，尽管其容量小。 在高速缓冲存储器控制电路中，检测处理器的访问操作是否针对存储器的特定区域，并且当数据要被从特定区域读出或被写入时， 数据被复制到高速缓冲存储器上，并且当数据要从其他区域读出时，立即执行存储器的操作而不等待缓存存储器的引用。 通过为要重复使用的数据分配特定区域，可以提供尽管容量小的高效率的高速缓冲存储器。 这种数据的代表性例子是堆栈中的数据。
-
-
-
-
-
-
-
-
-
搜索结果
36 条记录 (耗时 0.028 秒)
