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1.发明授权Multiprocessor system having a processor invalidating operand cache when lock-accessing 失效具有处理器的多处理器系统在锁定访问时使操作数缓存无效
公开(公告)号：US5740401A
公开(公告)日：1998-04-14
申请号：US9077
申请日：1993-01-26
CPC分类号： G06F9/52 , G06F12/0806 , G06F12/1466
摘要： A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.
摘要翻译： 多处理器系统包括地址总线170，数据总线180，处理器110和120，访问队列135和145，共享存储器130和140以及锁定控制电路500和510.特别地，锁定指示标志寄存器501是 当一个处理器110中的操作数高速缓存112正在对共享存储器130的预定地址进行锁定访问时，标志寄存器501是基于锁定命令信号260设置的， 在另一个处理器120中的指令高速缓存122到共享存储器130的预定地址的访问是被禁止的，但是在锁定访问时允许访问不同的地址。 在锁定访问被释放之后，锁定控制电路500接受对预定地址的访问。
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2.发明授权Single chip pipeline data processor using instruction and operand cache memories for parallel operation of instruction control and executions unit 失效单芯片流水线数据处理器采用指令和操作数缓存存储器，用于并行操作指令控制和执行单元
公开(公告)号：US4989140A
公开(公告)日：1991-01-29
申请号：US323125
申请日：1989-03-13
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，该指令控制单元具有从主存储器读出的第一相关存储器存储指令，以及指令控制器，当该指令为指令时，从第一关联存储器读出指令 存在于第一关联存储器中，并且当指令不存在于第一关联存储器中时，指令控制单元产生要执行的指令的输出。 指令执行单元具有第二关联存储器，其存储从主存储器读出的操作数数据，以及指令执行器，当所述操作数数据存在于所述第二关联存储器中时，通过使用从所述第二关联存储器读出的操作数据来执行所述指令; 当操作数数据不存在于第二关联存储器中时，从主存储器。
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3.发明授权Data processor capable of executing an instruction that makes a cache memory ineffective 失效能够执行使高速缓冲存储器无效的指令的数据处理器公开(公告)号：US06779102B2
公开(公告)日：2004-08-17
申请号：US09886267
申请日：2001-06-22
IPC分类号： G06F1578
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.
摘要翻译： 形成在LSI芯片上的数据处理器具有指令地址发生器，指令高速缓冲存储器，其具有各自存储指令地址的条目和与该指令地址对应的指令，指令译码器从对应于指令地址的所述高速缓冲存储器解码指令 所述指令地址生成器，响应于所述指令解码器的输出信号产生操作数地址的操作数地址生成器和具有条目的操作数高速缓存存储器，每个存储操作数地址和对应于其操作数地址的操作数数据。 数据处理器执行使得在所述指令高速缓冲存储器和所述操作数高速缓冲存储器两者中的条目无效的指令。
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公开(公告)号：US5253197A
公开(公告)日：1993-10-12
申请号：US580464
申请日：1990-09-11
申请人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Suzuki , Suguru Tachibana , Hisayuki Higuchi , Katsuhiro Shimohigashi , Takehisa Hayashi , Makoto Hanawa , Tadahiko Nishimukai
CPC分类号： G11C15/04 , G06F12/0895 , G06F12/1054 , Y02B60/1225
摘要： In a first embodiment of a CAM (Content Addressable Memory) or cache memory of the present invention disclosed herein, comparing information stored in a memory cell with comparison input information is accomplished in a comparison circuit without first converting a readout current from the memory cell into voltage information. In another embodiment, a matching detection between first stored information outputted from a first memory cell array and second stored information outputted from a second memory cell array is accomplished by an integrally formed sensing and matching detection circuit which is characterized as having both sensing and matching detection capabilities. That is, the sensing and matching detection circuit senses both stored information and thereafter detects matching based on a sensing result.
摘要翻译： 在本文公开的本发明的CAM（内容可寻址存储器）或高速缓冲存储器的第一实施例中，将存储在存储单元中的比较信息与比较输入信息进行比较，在比较电路中完成，而无需将来自存储单元的读出电流转换成 电压信息。 在另一个实施例中，从第一存储单元阵列输出的第一存储信息与从第二存储单元阵列输出的第二存储信息之间的匹配检测由一体形成的感测和匹配检测电路来实现，其特征在于具有检测和匹配检测 能力 也就是说，感测和匹配检测电路感测存储的信息，并且此后基于感测结果检测匹配。
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5.发明授权Microprocessor with a cache memory in which validity flags for first and second data areas are simultaneously readable 失效具有高速缓冲存储器的微处理器，其中第一和第二数据区的有效性标志同时可读
公开(公告)号：US4942521A
公开(公告)日：1990-07-17
申请号：US119919
申请日：1987-11-13
CPC分类号： G06F12/0862
摘要： When the access is effected sequentially such as the prefetching of an instruction or the restoration of a register in the stack region, the retrieval is effected simultaneously for the consecutive addresses and the result is stored. When the consecutive addresses are to be accessed, the hit is determined relying upon the result that is stored without effecting the cache memory reference. In the case of mishit, the external memory is readily accessed to shorten the overhead time required for the cache memory reference. Therefore, the access time can be shortened in average.
摘要翻译： 当顺序地进行访问，例如预取指令或恢复堆栈区域中的寄存器时，对连续的地址同时进行检索，并且存储结果。 当要访问连续地址时，根据存储的结果确定命中，而不影响缓存存储器引用。 在mishit的情况下，可以容易地访问外部存储器，以缩短高速缓存存储器引用所需的开销时间。 因此，可以平均缩短访问时间。
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公开(公告)号：US06272596B1
公开(公告)日：2001-08-07
申请号：US09396414
申请日：1999-09-15
IPC分类号： G06F1202
CPC分类号： G06F9/30047 , G06F9/30043 , G06F9/3802 , G06F9/3824 , G06F12/0848 , G06F12/0891
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的指令的输出。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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7.发明授权RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register 失效RISC系统能够通过旁路寄存器在一个时钟周期内同时执行数据互锁位移和算术/逻辑指令
公开(公告)号：US5269007A
公开(公告)日：1993-12-07
申请号：US609408
申请日：1990-11-05
申请人： Makoto Hanawa , Tadahiko Nishimukai
发明人： Makoto Hanawa , Tadahiko Nishimukai
IPC分类号： G06F9/38
CPC分类号： G06F9/3826 , G06F9/30167 , G06F9/3822 , G06F9/3824
摘要： First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file, an arithmetic and logic unit, and a shifter. A first comparator compares a destination field of the first instruction with a first source field of the second instruction. The shifter produces an output in association with immediate data of the first instruction, the output being ordinarily stored in a register file. However, when both inputs of the comparator are identical to each other, the output from the shifter is supplied to an input of the arithmetic and logic unit via a bypass signal transmission path.
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公开(公告)号：US5974533A
公开(公告)日：1999-10-26
申请号：US113550
申请日：1998-07-10
IPC分类号： G06F9/30 , G06F9/312 , G06F9/34 , G06F9/345 , G06F9/38 , G06F9/445 , G06F12/00 , G06F12/02 , G06F12/08 , G06F12/10 , G06F12/12 , G06F13/16 , G06F15/78
CPC分类号： G06F9/30047 , G06F12/0848 , G06F12/0891 , G06F9/30043 , G06F9/3802 , G06F9/3824
摘要： A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.
摘要翻译： 用于使用存储在主存储器中的操作数数据执行指令的数据处理器包括指令控制单元，其具有存储从主存储器读出的指令的第一关联存储器。 当指令存在于第一关联存储器中时，数据处理器还包括从第一关联存储器读取指令的指令控制器，并且当指令不存在于第一关联存储器中时，从主存储器读取指令。 控制器还具有要执行的输出指令。 指令执行单元具有存储从主存储器读出的操作数数据的第二关联存储器。 当操作数数据存在于第二关联存储器中时，当操作数数据不存在于第二关联存储器中时，指令执行器通过使用从第二关联存储器读出的操作数数据执行指令。
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9.发明授权Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction 失效用于选择性地同时执行延迟槽指令的数据处理器和在条件分支指令之后的第二后续指令
公开(公告)号：US5381531A
公开(公告)日：1995-01-10
申请号：US727581
申请日：1991-07-09
IPC分类号： G06F9/38
CPC分类号： G06F9/3822 , G06F9/30167 , G06F9/3836 , G06F9/3885
摘要： An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first and the second instruction thus fetched are set in a first and a second register (641, 642) before being decoded in a first and a second instruction decoder (644, 645). Comparators (131, 132) compares data on the destination field of the first instruction with data on the source field of the second instruction. When both the data are inconsistent, a parallel operation control unit (646) permits the first and the second instruction execution unit (651, 652) under the first and the second instruction to execute the two instructions in response to the outputs of the comparators (131, 132). When both the data are consistent, the parallel operation control unit (646) inhibits the parallel execution.
摘要翻译： 能够同时执行两个指令的数据处理器（610）的指令获取单元（640）在一个周期中从存储器（620）获取第一和第二指令。 在第一和第二指令解码器（644,645）中被解码之前，这样取得的第一和第二指令被设置在第一和第二寄存器（641,642）中。 比较器（131,132）将第一指令的目的地字段的数据与第二指令的源字段上的数据进行比较。 当两个数据不一致时，并行操作控制单元（646）允许第一和第二指令下的第一和第二指令执行单元（651,652）响应于比较器的输出执行两个指令（ 131,132）。 当两个数据一致时，并行操作控制单元（646）禁止并行执行。
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10.发明授权Multiprocessor system having shared memory divided into a plurality of banks with access queues corresponding to each bank 失效具有被分成多个存储体的共享存储器的多处理器系统具有对应于每个存储体的访问队列
公开(公告)号：US5375215A
公开(公告)日：1994-12-20
申请号：US784546
申请日：1991-10-29
IPC分类号： G06F15/16 , G06F12/00 , G06F12/06 , G06F13/16 , G06F15/167 , G06F15/177 , G06F13/36 , G06F9/40
CPC分类号： G06F13/1642 , G06F13/1605
摘要： A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access request need not wait for a previous access request to be finished. Accordingly, the throughput of the system can be improved greatly.
摘要翻译： 本发明的多处理器系统具有地址总线，数据总线，第一和第二处理器，四个访问队列和被划分为四个存储体的共享存储器。 四个访问队列由用于缓冲通过地址总线发送的多个访问请求地址的先进先出存储器构成。 即使连续访问请求被寻址到共享存储器的一个存储体，后续访问请求也不需要等待先前访问请求完成。 因此，可以大大提高系统的吞吐量。
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