公开(公告)号：US20090079008A1

公开(公告)日：2009-03-26

申请号：US12209270

申请日：2008-09-12

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

摘要： Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

摘要翻译： 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US06822297B2

公开(公告)日：2004-11-23

申请号：US09876292

申请日：2001-06-07

申请人： Mahalingam Nandakumar ,  Song Zhao ,  Youngmin Kim

发明人： Mahalingam Nandakumar ,  Song Zhao ,  Youngmin Kim

IPC分类号： H01L2362

CPC分类号： H01L29/6659 ,  H01L27/0266 ,  H01L29/1083 ,  H01L29/7833

摘要： A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions. According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping. In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It2, which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.

摘要翻译： p阱中的短沟道NMOS晶体管具有n源极和n沟道，每个包含延伸到晶体管栅极的浅区域，每个侧面由隔离区域横向限定并由沟道停止区域垂直地限定 以及从栅极凹陷的较深区域，并且当反向偏置时都具有耗尽区域。 浅区域部分地被增强的p掺杂注入口袋包围。 晶体管还在这些增强的p掺杂区域中具有比半导体其余部分高的p电阻率的另一区域。 这些区域大致从相应的浅区域的内部边界横向延伸到相应的凹陷区域的内部边界，并且从刚好在源极和漏极的耗尽区域的深度的深度垂直地延伸到接近通道停止区域的顶部。根据 本发明通过使用已经用于形成扩展的源极和漏极的植入物的相同的光掩模，通过补偿n掺杂的离子注入（例如砷或磷）在栅极定义之后产生这些较高p型电阻率的区域， 在ESD事件中，这些具有较高电阻率的区域增加了寄生横向npn双极晶体管的电流增益，从而提高了电流It2，从而使其具有破坏性的局部加热引起热击穿，从而提高了ESD鲁棒性。

公开(公告)号：US08659112B2

公开(公告)日：2014-02-25

申请号：US12967109

申请日：2010-12-14

申请人： Mahalingam Nandakumar ,  Amitabh Jain

发明人： Mahalingam Nandakumar ,  Amitabh Jain

IPC分类号： H01L21/70 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

摘要翻译： 形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。 与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。 包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。 源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。 在源极和漏极之间进行源极/漏极退火。

公开(公告)号：US20090166675A1

公开(公告)日：2009-07-02

申请号：US12346458

申请日：2008-12-30

申请人： Mahalingam Nandakumar

发明人： Mahalingam Nandakumar

IPC分类号： H01L29/737 ,  H01L21/265 ,  H01L21/337

CPC分类号： H01L21/02658 ,  H01L21/02667

摘要： This disclosure relates to strain engineering to improve the performance of semiconductor components that include a strained region of the semiconductor substrate. The disclosure involves the amorphization of the target region and the recrystallization of the atomic lattice whilst imposing a strain on the region. The region so formed will form a strained lattice, wherein the strain is uniformly distributed throughout the region, and which retains the intrinsic strain even if the source of the mechanical strain is removed. The disclosure includes methods for forming semiconductor substrates having strained regions (such as semiconductor components having a strained channel region) and semiconductor components formed thereby, as well as variations having various properties and advantages.

摘要翻译： 本公开涉及应变工程，以改善包括半导体衬底的应变区域的半导体部件的性能。 本公开涉及目标区域的非晶化和原子格子的再结晶，同时在该区域上施加应变。 这样形成的区域将形成应变格子，其中应变均匀地分布在整个区域中，并且即使去除了机械应变源，其也保留了本征应变。 本公开包括用于形成具有应变区域（例如具有应变通道区域的半导体部件）和由其形成的半导体部件的半导体衬底的方法以及具有各种性质和优点的变型。

公开(公告)号：US20090004805A1

公开(公告)日：2009-01-01

申请号：US11771269

申请日：2007-06-29

申请人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

发明人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC分类号： H01L21/336 ,  H01L23/58

CPC分类号： H01L29/7847 ,  H01L21/31155 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6659

摘要： A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and source/drain sidewalls. The method also includes performing a source/drain implant of the semiconductor wafer, forming a cap layer over the semiconductor wafer, and performing a source/drain anneal. In addition, the method includes performing a damage implant of the cap layer and removing the cap layer over the semiconductor wafer.

摘要翻译： 一种用于在半导体晶片上制造晶体管的方法包括提供包含栅极堆叠，延伸区域和源极/漏极侧壁的部分晶体管。 该方法还包括执行半导体晶片的源极/漏极注入，在半导体晶片上形成覆盖层，并执行源极/漏极退火。 此外，该方法包括执行盖层的损伤注入并去除半导体晶片上的覆盖层。

公开(公告)号：US07393787B2

公开(公告)日：2008-07-01

申请号：US11209140

申请日：2005-08-22

申请人： Hiroaki Niimi ,  Reima T. Laaksonen ,  Mahalingam Nandakumar

发明人： Hiroaki Niimi ,  Reima T. Laaksonen ,  Mahalingam Nandakumar

IPC分类号： H01L21/302

CPC分类号： H01L27/11 ,  H01L21/823462 ,  H01L21/823857 ,  H01L21/8249

摘要： The present invention provides a method for manufacturing a gate dielectric, a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit. The method for manufacturing the gate dielectric, without limitation, may include forming a nitrided dielectric layer (520) over a substrate (310), the nitrided dielectric layer (520) having a non-uniformity of nitrogen in a bulk thereof, and removing at least a portion of the nitrided dielectric layer (520) using a high temperature chemical treatment, the removing reducing the non-uniformity.

摘要翻译： 本发明提供一种栅极电介质的制造方法，半导体器件的制造方法以及集成电路的制造方法。 用于制造栅极电介质的方法，但不限于，可以包括在衬底（310）上形成氮化介电层（520），氮化介电层（520）在其主体中具有不均匀的氮，并且在 使用高温化学处理的氮化介电层（520）的至少一部分，去除减少不均匀性。

公开(公告)号：US06228725B1

公开(公告)日：2001-05-08

申请号：US09281543

申请日：1999-03-30

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Mark S. Rodder ,  Ih-Chin Chen

IPC分类号： H01L21336

CPC分类号： H01L29/66575 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/7838

摘要： A low power transistor (70, 70′) formed in a face of a semiconductor layer (86) of a first conductivity type. The transistor includes a source and drain regions (76, 78) of a second conductivity type formed in the face of the semiconductor layer, and a gate (72) insulatively disposed adjacent the face of the semiconductor layer and between the source and drain regions. A layer of counter doping (80, 80′) of the second conductivity type is formed adjacent to the face of the semiconductor layer generally between the source and drain regions. A first and second pockets (82, 84, 82′, 84′) of the first conductivity type may also be formed generally adjacent to the source and drain regions and the counter doped layer (80, 80′).

摘要翻译： 形成在第一导电类型的半导体层（86）的表面上的低功率晶体管（70,70'）。 晶体管包括形成在半导体层的表面上的第二导电类型的源极和漏极区域（76,78），以及邻近半导体层的表面并且在源极和漏极区域之间绝缘地设置的栅极（72）。 通常在源极和漏极区域之间形成与半导体层的表面相邻的第二导电类型的反向掺杂层（80,80'）。 第一导电类型的第一和第二凹穴（82,84,82'，84'）也可以大致相邻于源极和漏极区域以及反向掺杂层（80,80'）形成。

公开(公告)号：US07638402B2

公开(公告)日：2009-12-29

申请号：US11728928

申请日：2007-03-27

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

摘要翻译： 在形成晶体管时实现侧壁间隔器回拉方案。 除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。 较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。 该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。 这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。

公开(公告)号：US20090170277A1

公开(公告)日：2009-07-02

申请号：US12345414

申请日：2008-12-29

申请人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

发明人： Mahalingam Nandakumar ,  Wayne Bather ,  Narendra Singh Mehta

IPC分类号： H01L21/764 ,  H01L21/302

CPC分类号： H01L21/76254 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32139

摘要： A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.

摘要翻译： 提供一种用于半导体处理的方法，其中通过离子注入在结构上弱化一个或多个层来帮助去除一层或多层。 提供具有形成在其上的一个或多个初级层的半导体衬底，并且在一个或多个初级层上形成二次层。 一个或多个离子种类被注入到二次层中，其中结构上弱化了二次层，并且在二级层上形成图案化的光致抗蚀剂层。 除去未被图案化光致抗蚀剂层覆盖的二次层和一个或多个初级层的各部分，并进一步除去图案化的光致抗蚀剂层。 第二层的至少另一部分被去除，其中次级层的结构弱化增加了次级层的至少另一部分的去除速率。

公开(公告)号：US20080160708A1

公开(公告)日：2008-07-03

申请号：US11728928

申请日：2007-03-27

申请人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

发明人： Mahalingam Nandakumar ,  Amitava Chatterjee ,  Terrence J. Riley

IPC分类号： H01L21/336

CPC分类号： H01L21/823468 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.

摘要翻译： 在形成晶体管时实现侧壁间隔器回拉方案。 除了别的以外，该方案允许晶体管的硅化物区域变得更大，或者更具有更大的表面积。 较大的表面积具有较低的电阻，因此可以更精确地将电压施加到晶体管。 该方案还允许使晶体管稍薄，使得在晶体管上形成的介电材料层中的空隙的形成得到减轻。 这通过促进更可预测的或者其它期望的晶体管行为来缓解产量损失。