公开(公告)号：US08951863B2

公开(公告)日：2015-02-10

申请号：US13780591

申请日：2013-02-28

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L27/115 ,  H01L21/82 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L21/82 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。

公开(公告)号：US08933711B2

公开(公告)日：2015-01-13

申请号：US13228215

申请日：2011-09-08

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： G01R27/26 ,  G01T1/29

CPC分类号： G01T1/2907

摘要： A system that includes at least one capacitive sensor for least one angle of incidence component of radiation being measured striking the sensor. The measured capacitance of the sensor is affected by radiation striking the sensor. In some embodiments, the system includes multiple sensors where differences in the capacitive measurements of the sensors can be used to determine information about the radiation such as e.g. horizontal angle, directional angle, and dose.

摘要翻译： 一种系统，其包括至少一个电容传感器，用于至少一个被测量的辐射的入射角分量入射到传感器。 传感器的测量电容受到撞击传感器的辐射的影响。 在一些实施例中，系统包括多个传感器，其中可以使用传感器的电容测量值的差异来确定关于辐射的信息，例如， 水平角，方向角和剂量。

公开(公告)号：US08877601B2

公开(公告)日：2014-11-04

申请号：US12886859

申请日：2010-09-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/76

CPC分类号： H01L28/87 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.

摘要翻译： 在半导体衬底上形成有源器件区域。 互连层形成在有源器件区域上，其中互连层包括具有第一介电常数的第一介电材料，第一电介质材料中的第一金属互连和第一介电材料中的第二金属互连，并且横向间隔开 从第一个金属互连。 去除第一介电材料的一部分，使得第一电介质材料的剩余部分保留在互连层内，其中去除的部分从第一和第二金属互连之间的位置移除。 第一和第二金属互连之间的第一介电材料部分被去除的位置用第二介电常数填充，第二介电常数高于第一介电常数。

公开(公告)号：US08877568B2

公开(公告)日：2014-11-04

申请号：US13781727

申请日：2013-02-28

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/335 ,  H01L21/8232 ,  H01L27/115 ,  H01L21/28

CPC分类号： H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11539 ,  H01L27/11573 ,  Y10S977/773

摘要： Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned.

摘要翻译： 制造逻辑区域中的逻辑晶体管和衬底的NVM区域中的NVM单元的方法包括在栅极电介质上形成导电层，在NVM区域上形成导电层，在逻辑区域上去除导电层，形成 在NVM区域上的电介质层，在电介质层上形成保护层，从逻辑区域去除电介质层和保护层，在逻辑区域上形成高k电介质层，在保护层的剩余部分形成高介电常数， 以及在所述高k电介质层上形成第一金属层。 在NVM区域上去除第一金属层，高k电介质和保护层的剩余部分。 导电层沉积在电介质层的剩余部分上并在第一金属层之上，并且导电层被图案化。

公开(公告)号：US08716781B2

公开(公告)日：2014-05-06

申请号：US13907491

申请日：2013-05-31

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L29/792

CPC分类号： H01L27/04 ,  H01L21/28273 ,  H01L27/11534 ,  H01L27/11575 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer and barrier layer are formed over the control gate. A sacrificial layer is formed over the barrier layer and planarized. A first patterned masking layer is formed over the sacrificial layer and control gate in the NVM region which defines a select gate location laterally adjacent the control gate in the NVM region. A second masking layer is formed in the logic region which defines a logic gate location. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location which exposes the barrier layer.

公开(公告)号：US08716089B1

公开(公告)日：2014-05-06

申请号：US13790225

申请日：2013-03-08

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L21/8247

CPC分类号： H01L29/42344 ,  H01L27/11573 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/792

摘要： A thermal oxide is formed in an NVM region and a logic region. A polysilicon layer is formed over the thermal oxide and patterned to form a dummy gate and a select gate in the logic and NVM regions, respectively. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, forming an opening. A second dielectric layer is formed over the select gate and within the opening, and a gate layer is formed over the second dielectric layer and within the opening, wherein the gate layer within the opening forms a logic gate and the gate layer is patterned to form a control gate in the NVM region.

摘要翻译： 在NVM区域和逻辑区域中形成热氧化物。 多晶硅层形成在热氧化物的上方并被图案化以分别在逻辑和NVM区域中形成伪栅极和选择栅极。 第一电介质层形成在NVM和围绕选择栅极和虚拟栅极的逻辑区域中。 从NVM区域去除第一介电层并在逻辑区域中保护。 在选择栅极上形成电荷存储层。 去除虚拟门，形成开口。 在选择栅极和开口内形成第二电介质层，并且栅极层形成在第二电介质层上并且在开口内，其中开口内的栅极层形成逻辑门，栅极层被图案化以形成 NVM地区的控制门。

公开(公告)号：US08536006B2

公开(公告)日：2013-09-17

申请号：US13307719

申请日：2011-11-30

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/336

CPC分类号： H01L21/823842 ,  H01L27/11546 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7881

摘要： A method includes forming a gate dielectric over a substrate in an NVM region and a logic region; forming a first conductive layer over the gate dielectric in the NVM region and the logic region; patterning the first conductive layer in the NVM region to form a select gate; forming a charge storage layer over the select gate in the NVM region and the first conductive layer in the logic region; forming a second conductive layer over the charge storage layer in the NVM region and the logic region; removing the second conductive layer and the charge storage layer from the logic region; patterning the first conductive layer in the logic region to form a first logic gate; and after forming the first logic gate, patterning the second conductive layer in the NVM region to form a control gate which overlaps a sidewall of the select gate.

摘要翻译： 一种方法包括在NVM区域和逻辑区域中的衬底上形成栅极电介质; 在NVM区域和逻辑区域中的栅极电介质上形成第一导电层; 图案化NVM区域中的第一导电层以形成选择栅极; 在NVM区域的选择栅极和逻辑区域中的第一导电层上形成电荷存储层; 在NVM区域和逻辑区域中的电荷存储层上形成第二导电层; 从所述逻辑区域去除所述第二导电层和所述电荷存储层; 图案化逻辑区域中的第一导电层以形成第一逻辑门; 并且在形成第一逻辑门之后，对NVM区域中的第二导电层进行构图以形成与选择栅极的侧壁重叠的控制栅极。

公开(公告)号：US20130214346A1

公开(公告)日：2013-08-22

申请号：US13402426

申请日：2012-02-22

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42348

摘要： A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.

摘要翻译： 图案化第一导电层和底层电荷存储层，以在NVM区域中形成控制栅极。 第一介电层形成在控制栅上。 牺牲层形成在第一电介质层上并且被平坦化。 在牺牲层上形成图案化掩模层，该牺牲层包括限定在NVM区域中与控制栅极横向相邻的选择栅极位置的第一部分和在逻辑区域中限定逻辑门的第二部分。 去除牺牲层的暴露部分，使得第一部分保持在选择栅极位置。 在第一部分上形成第二电介质层并将其平坦化以暴露第一部分。 第一部分被去除以导致选择门位置处的打开。 在开口中形成栅介质层和选择栅极。

公开(公告)号：US08460996B2

公开(公告)日：2013-06-11

申请号：US11931565

申请日：2007-10-31

申请人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

发明人： Gauri V. Karve ,  Mark D. Hall ,  Srikanth B. Samavedam

IPC分类号： H01L21/8242

CPC分类号： H01L27/092 ,  H01L21/823807 ,  H01L21/823857 ,  H01L29/1054

摘要： An integrated circuit with devices having dielectric layers with different thicknesses. The dielectric layers include a high-k dielectric and some of the dielectric layers include an oxide layer that is formed from an oxidation process. Each device includes a layer including germanium or carbon located underneath the electrode stack of the device. A silicon cap layers is located over the layer including germanium or carbon.

摘要翻译： 具有具有不同厚度的电介质层的器件的集成电路。 电介质层包括高k电介质，并且一些电介质层包括由氧化工艺形成的氧化物层。 每个器件包括位于器件的电极堆叠下方的包含锗或碳的层。 硅层位于包含锗或碳的层之上。

公开(公告)号：US20120252171A1

公开(公告)日：2012-10-04

申请号：US13077501

申请日：2011-03-31

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/82

CPC分类号： H01L29/42324 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/11536 ,  H01L29/66825

摘要： A method for forming an integrated circuit for a non-volatile memory cell transistor is disclosed that includes: forming a layer of discrete storage elements over a substrate in a first region of the substrate and in a second region of the substrate; forming a first layer of dielectric material over the layer of discrete storage elements in the first region and the second region; forming a first layer of barrier work function material over the first layer of dielectric material in the first region and the second region; and removing the first layer of barrier work function material from the second region, the first layer of dielectric material from the second region, and the layer of discrete storage elements from the second region. After the removing, a second layer of barrier work function material is formed over the substrate in the first region and the second region. The second layer of barrier work function material is removed from the first region. A first gate of a memory device is formed in the first region. The first gate includes a portion of the first layer of barrier work function material. The memory device includes a charge storage structure including a portion of the layer of discrete storage elements. A second gate of a transistor is formed in the second region, the second gate including a portion of the second layer of barrier work function material.

摘要翻译： 公开了一种用于形成用于非易失性存储单元晶体管的集成电路的方法，其包括：在所述衬底的第一区域和所述衬底的第二区域中的衬底上形成离散存储元件层; 在所述第一区域和所述第二区域中的离散存储元件层上形成第一介电材料层; 在所述第一区域和所述第二区域中的所述第一介电材料层上形成阻挡功函数材料的第一层; 以及从所述第二区域去除所述第一层屏障功能材料，从所述第二区域去除所述第一介电材料层，以及从所述第二区域移除所述离散存储元件层。 在去除之后，在第一区域和第二区域中的衬底上形成第二层屏障功能材料层。 从第一区域去除第二层屏障功能材料。 存储器件的第一栅极形成在第一区域中。 第一栅极包括第一层屏障功能材料的一部分。 存储器件包括电荷存储结构，其包括离散存储元件层的一部分。 晶体管的第二栅极形成在第二区域中，第二栅极包括第二层屏障功能材料的一部分。