公开(公告)号：US20150279854A1

公开(公告)日：2015-10-01

申请号：US14228678

申请日：2014-03-28

申请人： MARK D. HALL ,  Mehul D. Shroff

发明人： MARK D. HALL ,  Mehul D. Shroff

IPC分类号： H01L27/115 ,  H01L21/306 ,  H01L21/321 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L27/11568 ,  H01L21/31051 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

摘要翻译： 在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。 在逻辑区域中，形成高k电介质和阻挡层。 在阻挡层和第一材料层之上形成第二栅极材料层。 图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。 栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。 在电荷存储层上的开口中形成控制栅极。 第二栅极材料层的部分被金属逻辑门替代。

公开(公告)号：US08951892B2

公开(公告)日：2015-02-10

申请号：US13539070

申请日：2012-06-29

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/02 ,  H01L29/66 ,  B82Y40/00

CPC分类号： H01L29/0676 ,  B60C23/00 ,  B81B1/00 ,  B81B2203/0361 ,  B82Y20/00 ,  B82Y30/00 ,  B82Y40/00 ,  G01L9/06 ,  G01N33/0031 ,  G02B6/107 ,  G02B6/126 ,  G02B2006/12097 ,  H01L21/3086 ,  H01L29/0665 ,  H01L29/66 ,  H01L33/18 ,  H01L41/1132 ,  H01L43/02

摘要： A disclosed method of fabricating a hybrid nanopillar device includes forming a mask on a substrate and a layer of nanoclusters on the hard mask. The hard mask is then etched to transfer a pattern formed by the first layer of nanoclusters into a first region of the hard mask. A second nanocluster layer is formed on the substrate. A second region of the hard mask overlying a second region of the substrate is etched to create a second pattern in the hard mask. The substrate is then etched through the hard mask to form a first set of nanopillars in the first region of the substrate and a second set of nanopillars in the second region of the substrate. By varying the nanocluster deposition steps between the first and second layers of nanoclusters, the first and second sets of nanopillars will exhibit different characteristics.

摘要翻译： 公开的制造混合纳米柱装置的方法包括在基底上形成掩模和硬掩模上的纳米团簇层。 然后蚀刻硬掩模以将由第一层纳米团簇形成的图案转移到硬掩模的第一区域中。 在基板上形成第二纳米团簇层。 蚀刻覆盖衬底的第二区域的硬掩模的第二区域，以在硬掩模中产生第二图案。 然后将衬底通过硬掩模蚀刻以在衬底的第一区域中形成第一组纳米柱，并在衬底的第二区域中形成第二组纳米柱。 通过改变第一和第二层纳米团簇之间的纳米团簇沉积步骤，第一组和第二组纳米颗粒将呈现不同的特征。

公开(公告)号：US08906764B2

公开(公告)日：2014-12-09

申请号：US13441426

申请日：2012-04-06

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over an NVM work function setting metal, the NVM work function setting metal is on a high-k dielectric, and a metal logic gate of a logic transistor is similarly formed over work function setting and high-k dielectric materials. The logic transistor is formed while portions of the metal select gate of the NVM cell are formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在NVM工作功能设定金属上，NVM工作功能设定金属位于高k电介质上，逻辑晶体管的金属逻辑门类似地形成工作功能设定和高电平 -k电介质材料。 在形成NVM单元的金属选择栅极的部分的同时形成逻辑晶体管。 在形成NVM单元的同时，保护逻辑晶体管，包括使用纳米晶体形成电荷存储区域，并在金属选择栅极的一部分上形成金属控制栅极以及在基板上的电荷存储区域的一部分。 蚀刻电荷存储区域以与金属控制栅极对准。

公开(公告)号：US08564044B2

公开(公告)日：2013-10-22

申请号：US13077491

申请日：2011-03-31

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L29/788 ,  H01L21/70 ,  H01L21/4763

CPC分类号： H01L29/42344 ,  B82Y10/00 ,  H01L21/28273 ,  H01L27/11536 ,  H01L29/42328 ,  H01L29/42332

摘要： An integrated circuit is disclosed that includes a split gate memory device comprising a select gate is located over a substrate. A charge storage layer includes a layer of discrete storage elements and a layer of high-k dielectric material covering at least one side of the layer of discrete storage elements. At least a portion of a control gate is located over the charge storage layer. The control gate includes a layer of barrier work function material and a layer of gate material located over the layer of barrier work function material.

摘要翻译： 公开了一种集成电路，其包括分离栅极存储器件，其包括位于衬底上方的选择栅极。 电荷存储层包括分立的存储元件层和覆盖分立存储元件层的至少一侧的高k电介质材料层。 控制栅极的至少一部分位于电荷存储层上方。 控制门包括一层屏障功能材料和位于屏障功能材料层之上的一层栅极材料。

公开(公告)号：US08536007B2

公开(公告)日：2013-09-17

申请号：US13402426

申请日：2012-02-22

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： H01L21/8246

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42348

摘要： A first conductive layer and an underlying charge storage layer are patterned to form a control gate in an NVM region. A first dielectric layer is formed over the control gate. A sacrificial layer is formed over the first dielectric layer and planarized. A patterned masking layer is formed over the sacrificial layer which includes a first portion which defines a select gate location laterally adjacent the control gate in the NVM region and a second portion which defines a logic gate in a logic region. Exposed portions of the sacrificial layer are removed such that a first portion remains at the select gate location. A second dielectric layer is formed over the first portion and planarized to expose the first portion. The first portion is removed to result in an opening at the select gate location. A gate dielectric layer and a select gate are formed in the opening.

摘要翻译： 图案化第一导电层和底层电荷存储层，以在NVM区域中形成控制栅极。 第一介电层形成在控制栅上。 牺牲层形成在第一电介质层上并且被平坦化。 在牺牲层上形成图案化掩模层，该牺牲层包括限定在NVM区域中与控制栅极横向相邻的选择栅极位置的第一部分和在逻辑区域中限定逻辑门的第二部分。 去除牺牲层的暴露部分，使得第一部分保持在选择栅极位置。 在第一部分上形成第二电介质层并将其平坦化以暴露第一部分。 第一部分被去除以导致选择门位置处的打开。 在开口中形成栅介质层和选择栅极。

公开(公告)号：US07491630B2

公开(公告)日：2009-02-17

申请号：US11375768

申请日：2006-03-15

申请人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

发明人： Mehul D. Shroff ,  Paul A. Grudowski ,  Mark D. Hall ,  Tab A. Stephens

IPC分类号： H01L21/04

CPC分类号： H01L21/82345 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462

摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。 虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63） 漏极注入步骤（71,77,91,97）和栅极蚀刻之后。

公开(公告)号：US08951863B2

公开(公告)日：2015-02-10

申请号：US13780591

申请日：2013-02-28

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L27/115 ,  H01L21/82 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L21/82 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/7881

摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. In an NVM region, a polysilicon select gate of the NVM cell is formed over a first thermally-grown oxygen-containing layer, and in a logic region, a work-function-setting material is formed over a high-k dielectric and a polysilicon dummy gate is formed over the work-function-setting material. Source/drains, a sidewall spacer, and silicided regions of the logic transistor are formed after the first thermally-grown oxygen-containing layer is formed. The polysilicon dummy gate is replaced by a metal gate. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region.

摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 在NVM区域中，在第一热生长含氧层上形成NVM单元的多晶硅选择栅极，在逻辑区域中，在高k电介质和多晶硅上形成功函数设定材料 在工作功能设置材料上形成虚拟门。 在形成第一热生长含氧层之后形成源极/漏极，侧壁间隔物和逻辑晶体管的硅化物区域。 多晶硅虚拟栅极由金属栅极代替。 在形成电荷存储区域的同时形成NVM单元时，保护逻辑晶体管。

公开(公告)号：US08933711B2

公开(公告)日：2015-01-13

申请号：US13228215

申请日：2011-09-08

申请人： Mark D. Hall ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Mehul D. Shroff

IPC分类号： G01R27/26 ,  G01T1/29

CPC分类号： G01T1/2907

摘要： A system that includes at least one capacitive sensor for least one angle of incidence component of radiation being measured striking the sensor. The measured capacitance of the sensor is affected by radiation striking the sensor. In some embodiments, the system includes multiple sensors where differences in the capacitive measurements of the sensors can be used to determine information about the radiation such as e.g. horizontal angle, directional angle, and dose.

摘要翻译： 一种系统，其包括至少一个电容传感器，用于至少一个被测量的辐射的入射角分量入射到传感器。 传感器的测量电容受到撞击传感器的辐射的影响。 在一些实施例中，系统包括多个传感器，其中可以使用传感器的电容测量值的差异来确定关于辐射的信息，例如， 水平角，方向角和剂量。

公开(公告)号：US08877601B2

公开(公告)日：2014-11-04

申请号：US12886859

申请日：2010-09-21

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/76

CPC分类号： H01L28/87 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： An active device region is formed in and on a semiconductor substrate. An interconnect layer is formed over the active device region, wherein the interconnect layer comprises a first dielectric material having a first dielectric constant, a first metal interconnect in the first dielectric material, and a second metal interconnect in the first dielectric material and laterally spaced apart from the first metal interconnect. A portion of the first dielectric material is removed such that a remaining portion of the first dielectric material remains within the interconnect layer, wherein the removed portion is removed from a location between the first and second metal interconnects. The location between the first and second metal interconnects from which the portion of the first dielectric material was removed is filled with a second dielectric material having a second dielectric constant, the second dielectric constant being higher than the first dielectric constant.

摘要翻译： 在半导体衬底上形成有源器件区域。 互连层形成在有源器件区域上，其中互连层包括具有第一介电常数的第一介电材料，第一电介质材料中的第一金属互连和第一介电材料中的第二金属互连，并且横向间隔开 从第一个金属互连。 去除第一介电材料的一部分，使得第一电介质材料的剩余部分保留在互连层内，其中去除的部分从第一和第二金属互连之间的位置移除。 第一和第二金属互连之间的第一介电材料部分被去除的位置用第二介电常数填充，第二介电常数高于第一介电常数。

公开(公告)号：US08877568B2

公开(公告)日：2014-11-04

申请号：US13781727

申请日：2013-02-28

申请人： Mehul D. Shroff ,  Mark D. Hall

发明人： Mehul D. Shroff ,  Mark D. Hall

IPC分类号： H01L21/335 ,  H01L21/8232 ,  H01L27/115 ,  H01L21/28

CPC分类号： H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11539 ,  H01L27/11573 ,  Y10S977/773

摘要： Methods of making a logic transistor in a logic region and an NVM cell in an NVM region of a substrate include forming a conductive layer on a gate dielectric, patterning the conductive layer over the NVM region, removing the conductive layer over the logic region, forming a dielectric layer over the NVM region, forming a protective layer over the dielectric layer, removing the dielectric layer and the protective layer from the logic region, forming a high-k dielectric layer over the logic region and a remaining portion of the protective layer, and forming a first metal layer over the high-k dielectric layer. The first metal layer, the high-k dielectric, and the remaining portion of the protective layer are removed over the NVM region. A conductive layer is deposited over the remaining portions of the dielectric layer and over the first metal layer, and the conductive layer is patterned.

摘要翻译： 制造逻辑区域中的逻辑晶体管和衬底的NVM区域中的NVM单元的方法包括在栅极电介质上形成导电层，在NVM区域上形成导电层，在逻辑区域上去除导电层，形成 在NVM区域上的电介质层，在电介质层上形成保护层，从逻辑区域去除电介质层和保护层，在逻辑区域上形成高k电介质层，在保护层的剩余部分形成高介电常数， 以及在所述高k电介质层上形成第一金属层。 在NVM区域上去除第一金属层，高k电介质和保护层的剩余部分。 导电层沉积在电介质层的剩余部分上并在第一金属层之上，并且导电层被图案化。