公开(公告)号：US20070008202A1

公开(公告)日：2007-01-11

申请号：US11473602

申请日：2006-06-23

申请人： Giuseppe Puma

发明人： Giuseppe Puma

IPC分类号： H03M3/00

CPC分类号： H04L25/49 ,  H03M7/3022 ,  H04L27/367

摘要： A sigma-delta converter has a signal input for receiving a data word. A clock signal input is designed to supply a clock signal. The sigma-delta converter includes a first clocked-operation accumulator stage whose input side is connected to the signal input, and at least one second clocked-operation accumulator stage connected in series with the first accumulator stage, with its input side coupled to an accumulator output of the first accumulator stage. The sigma-delta converter is configured to process the data word upon each clock signal only in one accumulator stage in the first and the at least one second accumulator stage, and output the processed data word at the accumulator output of the one accumulator stage. As a result, a time-critical response during signal processing is limited just to the accumulator stage which is currently processing the data word.

公开(公告)号：US20060202768A1

公开(公告)日：2006-09-14

申请号：US11432042

申请日：2006-05-11

申请人： Giuseppe Puma ,  Elmar Wagner

发明人： Giuseppe Puma ,  Elmar Wagner

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03L7/081

摘要： The invention is directed to a phase locked loop with a ΣΔ modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ΣΔ modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

摘要翻译： 本发明涉及一种带有SigmaDelta调制器的锁相环。 PLL的反馈路径中的多模除法器由SigmaDelta调制器驱动。 后者具有可以通过拉普拉斯平面中的复传递函数H（s）来描述的设计，所述传递函数具有复共轭对的极点。 该布置允许显着降低关键频域中的噪声，并且因此即使当PLL带宽与调制带宽一样大时，也允许基于无线电规范来遵守传输掩模。

公开(公告)号：US20060152292A1

公开(公告)日：2006-07-13

申请号：US11298010

申请日：2005-12-09

申请人： Giuseppe Puma ,  Duyen Pham-Stabner ,  Georg Stabner

发明人： Giuseppe Puma ,  Duyen Pham-Stabner ,  Georg Stabner

IPC分类号： H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1243 ,  H03B2200/0048 ,  H03B2200/005

摘要： A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance element (22) is formed by one or more varactors whose capacitance can be adjusted by an analogue adjusting voltage (Vtune), while a second capacitance element (23) is formed by an arrangement comprising a plurality of capacitors which can be actuated by a digital bit word VCWD[N:1]. Digital calibration for the VCO (20) is performed by determining whether the present adjusting voltage is within a particular voltage range and, if this is not the case, the digital bit word being incremented or decremented by a bit value.

摘要翻译： VCO电路（20）具有线圈（21）并且与其并联，具有恒定电容（24）和可调电容元件（22,23）。 第一电容元件（22）由一个或多个变容二极管形成，其中电容可以通过模拟调整电压（V调谐）来调节，而第二电容元件（23）由包括 可由数字位字VCWD [N：1]驱动的多个电容器。 通过确定当前的调整电压是否在特定电压范围内来执行VCO（20）的数字校准，如果不是这种情况，则数字位字被增加或减少位值。

公开(公告)号：US20050212605A1

公开(公告)日：2005-09-29

申请号：US11077635

申请日：2005-03-11

申请人： Giuseppe Puma

发明人： Giuseppe Puma

IPC分类号： H03C3/09 ,  H03L7/00 ,  H03L7/089 ,  H03L7/093 ,  H03L7/197

CPC分类号： H03C3/0925 ,  H03C3/0933 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/1976

摘要： The phase locked loop according to the invention has an adjustable charge pump (2) which is intended to generate a control voltage (UVCO). A voltage-controlled oscillator (4) and an evaluation unit (14) are connected downstream of said charge pump. In this case, the evaluation unit (14) is designed in such a manner that it can be used to generate a correction signal (Iref) using the control voltage (UVCO) and a nominal gradient ({circumflex over (K)} vco) of the voltage-controlled oscillator (4) and to apply said signal to the evaluation output. The latter is, in turn, connected to an input of the charge pump (2).

摘要翻译： 根据本发明的锁相环具有用于产生控制电压（UVCO）的可调电荷泵（2）。 电压控制振荡器（4）和评估单元（14）连接在所述电荷泵的下游。 在这种情况下，评估单元14被设计成可以使用控制电压（UVCO）和压控振荡器的标称梯度（K vco）来产生校正信号（Iref） （4）并将所述信号应用于评估输出。 后者又连接到电荷泵（2）的输入端。

公开(公告)号：US20070116160A1

公开(公告)日：2007-05-24

申请号：US11592423

申请日：2006-11-03

申请人： Carsten Eisenhut ,  Jens Kissing ,  Giuseppe Puma ,  Dietolf Seippel ,  Nenad Stevanovic

发明人： Carsten Eisenhut ,  Jens Kissing ,  Giuseppe Puma ,  Dietolf Seippel ,  Nenad Stevanovic

IPC分类号： H04L27/08

CPC分类号： H04W52/028 ,  Y02D70/144

摘要： A first signal path having an amplifier and a second signal path having an amplifier with adjustable gain factor are provided. A signal applied to the first and second signal paths is amplified and demodulated on the first signal path. Concurrently, the signal is amplified on the second signal path with a gain factor, and a power of the signal amplified by the second signal path is determined and used for determining the gain factor. A signal conditioning circuit has first and second signal paths and a first and a second operating state. In the first operating state, the first signal path is arranged for amplification for a demodulation, and the second signal path is arranged for amplification for determination of a power of the signal present. In the second operating state, one of the two signal paths is inactive and the other is arranged for demodulating the signal present.

摘要翻译： 提供了具有放大器和具有可调增益因子的放大器的第二信号路径的第一信号路径。 施加到第一和第二信号路径的信号在第一信号路径上被放大和解调。 同时，以增益因子在第二信号路径上放大信号，确定由第二信号路径放大的信号的功率，并用于确定增益因子。 信号调理电路具有第一和第二信号路径以及第一和第二操作状态。 在第一操作状态下，第一信号路径被布置用于解调的放大，并且第二信号路径被布置用于放大以确定存在的信号的功率。 在第二操作状态下，两个信号路径中的一个是无效的，另一个被布置用于解调存在的信号。

公开(公告)号：US20060171484A1

公开(公告)日：2006-08-03

申请号：US11303175

申请日：2005-12-16

申请人： Giuseppe Puma

发明人： Giuseppe Puma

IPC分类号： H04L27/20

CPC分类号： H03F3/24 ,  H03C5/00 ,  H03F2200/331 ,  H03F2200/351 ,  H03K7/08 ,  H04L27/361

摘要： A polar modulator contains a phase locked loop which is designed to emit a radio-frequency signal at one frequency to one output, with the frequency being derived from the reference signal and from a phase modulation signal at a control input of the phase locked loop. The modulator additionally has a second signal input for supplying an amplitude modulation signal. The second signal input is connected to a control input of a pulse width modulator, one of whose signal inputs is coupled to the output of the phase locked loop. The pulse width modulator is designed to vary the duty ratio of a signal which is applied to the signal input, with this variation being adjustable via a regulation signal at the control input. A filter can be connected downstream from the output of the pulse width modulator and suppresses higher harmonic components in a signal which can be tapped off at the output of the pulse width modulator. The amplitude of an output signal is thus modulated by carrying out pulse width modulation and by subsequent suppression of higher-level frequency components.

摘要翻译： 极性调制器包含锁相环，其被设计为以一个频率向一个输出发射射频信号，频率是从参考信号和相位调制信号在锁相环的控制输入端导出的。 调制器还具有用于提供幅度调制信号的第二信号输入。 第二信号输入连接到脉宽调制器的控制输入端，其中一个信号输入端耦合到锁相环路的输出。 脉冲宽度调制器被设计为改变施加到信号输入端的信号的占空比，该变化通过控制输入端的调节信号来调节。 滤波器可以连接到脉冲宽度调制器的输出端的下游，并抑制信号中的高次谐波分量，该信号可以在脉冲宽度调制器的输出端被分接。 因此，通过执行脉冲宽度调制和随后抑制较高电平的频率分量来调制输出信号的幅度。

公开(公告)号：US20060017511A1

公开(公告)日：2006-01-26

申请号：US11145821

申请日：2005-06-06

申请人： Giuseppe Puma ,  Elmar Wagner

发明人： Giuseppe Puma ,  Elmar Wagner

IPC分类号： H03L7/00

CPC分类号： H03L7/1976 ,  H03L7/081

摘要： The invention is directed to a phase locked loop with a ΣΔ modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ΣΔ modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

公开(公告)号：US20050141411A1

公开(公告)日：2005-06-30

申请号：US11017522

申请日：2004-12-20

申请人： Martin Friedrich ,  Christian Grewing ,  Giuseppe Puma ,  Christoph Sandner ,  Andreas Wiesbauer ,  Kay Winterberg ,  Stefan Waasen

发明人： Martin Friedrich ,  Christian Grewing ,  Giuseppe Puma ,  Christoph Sandner ,  Andreas Wiesbauer ,  Kay Winterberg ,  Stefan Waasen

IPC分类号： G10L19/00 ,  H04L27/38 ,  H04S3/00

CPC分类号： H04S3/00

摘要： A method and an arrangement for processing a received signal which comprises phase-shift modulated or amplitude-quadrature modulated part-signals which are transmitted in a plurality of different frequency bands, wherein the received signal is processed in a plurality of stages in succession, by multiplying all the input signals to each of the stages by two mutually orthogonal signals in each case to form two intermediate signals in each case, wherein the intermediate signals from one stage in each case act as the input signals to whichever is the succeeding stage in the particular case and the received signal acts as the input signal to the first stage, and wherein an in-phase and/or an quadrature component of the individual part-signals in the different frequency bands are determined from the intermediate signals from the last stage. Parallel, simultaneous reception of a plurality of frequency bands can be implemented relatively easily in this way.

摘要翻译： 一种用于处理接收信号的方法和装置，其包括在多个不同频带中发送的相移调制或幅度正交调制部分信号，其中接收信号以多个级连续地被处理，由 在每种情况下，将每个级的所有输入信号乘以两个相互正交的信号，以在每种情况下形成两个中间信号，其中来自一个级的中间信号在每种情况下都用作输入信号， 特定情况和接收信号充当到第一级的输入信号，并且其中根据最后级的中间信号确定不同频带中各个部分信号的同相和/或正交分量。 可以以这种方式相对容易地实现并行地同时接收多个频带。

公开(公告)号：US20050099198A1

公开(公告)日：2005-05-12

申请号：US10941428

申请日：2004-09-15

申请人： Giuseppe Puma ,  Duyen Pham-Stabner ,  Elmar Wagner

发明人： Giuseppe Puma ,  Duyen Pham-Stabner ,  Elmar Wagner

IPC分类号： G01R27/26 ,  G01R31/27 ,  G01R31/28 ,  G01R31/3167 ,  G01R31/3187 ,  H03M1/10 ,  G01R31/02

CPC分类号： H03M1/1071 ,  G01R27/2605 ,  G01R31/27 ,  G01R31/2851 ,  G01R31/3167 ,  G01R31/3187

摘要： An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically charging and discharging at least one of the capacitances. In this arrangement, the cycle frequency is dependent on the value of the capacitance. The cycle frequency or a quantity characteristic associated therewith is measured by a means to ascertain a value of the capacitance under test.

摘要翻译： 用于测试集成电路的电容阵列中的多个电容的装置包括电源和用于循环充电和放电至少一个电容的装置。 在这种布置中，周期频率取决于电容的值。 通过确定被测电容值的方法来测量与其相关联的循环频率或量特性。

公开(公告)号：US20070111691A1

公开(公告)日：2007-05-17

申请号：US11593283

申请日：2006-11-06

申请人： Andre Hanke ,  Giuseppe Puma

发明人： Andre Hanke ,  Giuseppe Puma

IPC分类号： H04B1/06 ,  H04B1/18 ,  H04B1/16

CPC分类号： H04B1/406 ,  H03H11/1291 ,  H03H2011/0494 ,  H04B1/005

摘要： The invention discloses a signal conditioning circuit having a vector demodulator for breaking down a signal applied to the input into a first component and a second component. The outputs of the vector demodulator having at least one first amplifier circuit comprising a first and a second input connected thereto which may be configured to amplify signals applied to the input using an adjustable gain. The outputs of the at least one first amplifier circuit are connected to a first analog/digital converter. A polyphase filter may be connected between outputs of the vector demodulator and the input of the first amplifier circuit. The polyphase filter has an adjustable filter bandwidth.

摘要翻译： 本发明公开了一种具有矢量解调器的信号调理电路，用于将施加到输入端的信号分解为第一分量和第二分量。 矢量解调器的输出具有至少一个第一放大器电路，其包括与其连接的第一和第二输入，该第一和第二输入可被配置为利用可调增益来放大施加到输入端的信号。 所述至少一个第一放大器电路的输出连接到第一模拟/数字转换器。 多相滤波器可以连接在矢量解调器的输出端和第一放大器电路的输入端之间。 多相滤波器具有可调滤波器带宽。