公开(公告)号：US08530894B2

公开(公告)日：2013-09-10

申请号：US13474934

申请日：2012-05-18

申请人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

发明人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US07713763B2

公开(公告)日：2010-05-11

申请号：US12132014

申请日：2008-06-03

申请人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

发明人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L21/00

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US20090001371A1

公开(公告)日：2009-01-01

申请号：US12026273

申请日：2008-02-05

申请人： Anthony Mowry ,  Markus Lenski ,  Andy Wei ,  Roman Boschke

发明人： Anthony Mowry ,  Markus Lenski ,  Andy Wei ,  Roman Boschke

IPC分类号： H01L29/04 ,  H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

摘要： A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.

摘要翻译： 提出了一种技术，其提供晶体管的源极/漏极区域的选择性预非晶化，同时防止晶体管的栅电极的前非晶化。 示例性实施例包括在栅电极上形成预非晶化注入阻挡材料。 进一步的说明性实施例包括通过使用各种压力源在通道区域中诱导应变。

公开(公告)号：US20070122966A1

公开(公告)日：2007-05-31

申请号：US11468450

申请日：2006-08-30

申请人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

发明人： Jan Hoentschel ,  Andy Wei ,  Markus Lenski ,  Peter Javorka

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7843

摘要： A method and a semiconductor device are provided in which respective contact layers having a specific intrinsic stress may be directly formed on respective metal silicide regions without undue metal silicide degradation during an etch process for removing an unwanted portion of an initially deposited contact layer. Moreover, due to the inventive concept, the strain-inducing contact layers may be formed directly on the respective substantially L-shaped spacer elements, thereby enhancing even more the stress transfer mechanism.

摘要翻译： 提供了一种方法和半导体器件，其中具有特定固有应力的各个接触层可以直接形成在各自的金属硅化物区域上，而在用于去除最初沉积的接触层的不希望的部分的蚀刻工艺期间不会有不适当的金属硅化物降解。 此外，由于本发明构思，应变感应接触层可以直接形成在相应的大致L形间隔元件上，从而进一步增强应力传递机构。

公开(公告)号：US20060246641A1

公开(公告)日：2006-11-02

申请号：US11288673

申请日：2005-11-29

申请人： Thorsten Kammler ,  Andy Wei ,  Markus Lenski

发明人： Thorsten Kammler ,  Andy Wei ,  Markus Lenski

IPC分类号： H01L21/338

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

摘要翻译： 通过去除用于形成高度复杂的横向掺杂剂分布的外部间隔物，在形成金属硅化物之前，获得与常规方法的高度的工艺相容性，同时可以将接触衬垫层定位更多 与通道区域紧密相连，从而允许用于在通道区域中产生相应应变的高效应力传递机构。

公开(公告)号：US20120223309A1

公开(公告)日：2012-09-06

申请号：US13474934

申请日：2012-05-18

申请人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

发明人： Anthony Mowry ,  Casey Scott ,  Vassilios Papageorgiou ,  Andy Wei ,  Markus Lenski ,  Andreas Gehring

IPC分类号： H01L23/58

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L22/34 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833

摘要： By providing a test structure for evaluating the patterning process and/or the epitaxial growth process for forming embedded semiconductor alloys in sophisticated semiconductor devices, enhanced statistical relevance in combination with reduced test time may be accomplished.

摘要翻译： 通过提供用于评估用于在复杂半导体器件中形成嵌入式半导体合金的图案化工艺和/或外延生长工艺的测试结构，可以实现与减少的测试时间相结合的增强的统计相关性。

公开(公告)号：US07879667B2

公开(公告)日：2011-02-01

申请号：US12026273

申请日：2008-02-05

申请人： Anthony Mowry ,  Markus Lenski ,  Andy Wei ,  Roman Boschke

发明人： Anthony Mowry ,  Markus Lenski ,  Andy Wei ,  Roman Boschke

IPC分类号： H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/8238 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7848

摘要： A technique is presented which provides for a selective pre-amorphization of source/drain regions of a transistor while preventing pre-amorphization of a gate electrode of the transistor. Illustrative embodiments include the formation of a pre-amorphization implant blocking material over the gate electrode. Further illustrative embodiments include inducing a strain in a channel region by use of various stressors.

摘要翻译： 提出了一种技术，其提供晶体管的源极/漏极区域的选择性预非晶化，同时防止晶体管的栅电极的前非晶化。 示例性实施例包括在栅电极上形成预非晶化注入阻挡材料。 进一步的说明性实施例包括通过使用各种压力源在通道区域中诱导应变。

公开(公告)号：US07354838B2

公开(公告)日：2008-04-08

申请号：US11288673

申请日：2005-11-29

申请人： Thorsten Kammler ,  Andy Wei ,  Markus Lenski

发明人： Thorsten Kammler ,  Andy Wei ,  Markus Lenski

IPC分类号： H01L21/336

CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： By removing an outer spacer, used for the formation of highly complex lateral dopant profiles, prior to the formation of metal silicide, a high degree of process compatibility with conventional processes is obtained, while at the same time a contact liner layer may be positioned more closely to the channel region, thereby allowing a highly efficient stress transfer mechanism for creating a corresponding strain in the channel region.

摘要翻译： 通过去除用于形成高度复杂的横向掺杂剂分布的外部间隔物，在形成金属硅化物之前，获得与常规工艺的高度的工艺相容性，同时可以将接触衬垫层定位更多 与通道区域紧密相连，从而允许用于在通道区域中产生相应应变的高效应力传递机构。

公开(公告)号：US08987144B2

公开(公告)日：2015-03-24

申请号：US13198107

申请日：2011-08-04

申请人： Stephan Kronholz ,  Markus Lenski ,  Hans-Juergen Thees

发明人： Stephan Kronholz ,  Markus Lenski ,  Hans-Juergen Thees

IPC分类号： H01L21/302 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3115

CPC分类号： H01L21/823864 ,  H01L21/31116 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.

摘要翻译： 在复杂的半导体器件中，高k金属栅极电极结构可以在早期制造阶段形成，其中敏感栅极材料的完整性通过在选定的活性区域中选择性沉积应变诱导半导体材料之后提供附加的衬垫材料。 此外，可以基于通过避免图案化和去除任何牺牲氧化物间隔物而显着降低隔离区域和有源区域中的材料侵蚀程度的工艺流程来去除栅电极结构的电介质盖材料。

公开(公告)号：US08835298B2

公开(公告)日：2014-09-16

申请号：US13415492

申请日：2012-03-08

申请人： Sivakumar Kumarasamy ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

发明人： Sivakumar Kumarasamy ,  Clemens Fitz ,  Markus Lenski ,  Jochen Poth ,  Kristin Schupke

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/28518 ,  H01L22/12 ,  H01L22/20

摘要： The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni′/Pt layer at a temperature of 130° C.

摘要翻译： 如果检测到Pt残留物，则通过执行包括在SWC工具中在130℃的温度下施加SPM的返工来减少形成含Pt的NiSi后剩余的Pt残余物的量。 实施例包括在半导体衬底上沉积一层Ni / Pt，退火沉积的Ni / Pt层，从退火的Ni / Pt层去除未反应的Ni，退火Ni去除的Ni / Pt层，从退火的Ni中除去未反应的Pt Ni / Pt层，分析未去除Pt残留物的Pt去除Ni / Pt层，如果检测到未反应的Pt残留物，则在SWC工具中将Pt施加到去除的Pt / Ni层上。 可以在130℃的温度下将SPM施加到Pt去除的Ni'/ Pt层上