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公开(公告)号：US6104626A
公开(公告)日：2000-08-15
申请号：US808866
申请日：1997-02-28
申请人： Masayuki Katakura , Masashi Takeda
发明人： Masayuki Katakura , Masashi Takeda
摘要： An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1 Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.
摘要翻译： 一种包括模拟存储电路的模拟延迟电路，其中包括存储电容器和用于存储电容器的选择开关的多个存储单元被布置成矩阵，包括为各个列提供的行开关，用于单独由行选择信号驱动 。 来自时钟发生电路的相同时钟信号被共同地提供给X方向扫描电路和Y方向扫描电路。 X方向扫描电路的寄存器的级数和Y方向扫描电路的寄存器的级数被设置为使得它们除了1之外没有公共除数。因此，当要选择性地扫描存储器单元时， 可以在不依赖于存储单元的位置的情况下，向所有存储单元提供相同的选择条件，并且减少连接到信号写入/读取端子的寄生电容。
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12.发明授权Noise reduction circuit with a main signal path and auxiliary signal path having a high pass filter characteristic 失效具有主信号路径和辅助信号路径的降噪电路具有高通滤波器特性
公开(公告)号：US4547741A
公开(公告)日：1985-10-15
申请号：US497415
申请日：1983-05-24
申请人： Masayuki Katakura
发明人： Masayuki Katakura
摘要： A noise reduction circuit has a main signal path and an auxiliary signal path having the characteristics of a high-pass filter with a controllable cut-off frequency, a control circuit varies the cut-off frequency of the high-pass filter as a function of the auxiliary signal path output. The auxiliary signal path current is derived as a current source output so that the summing of the main signal and auxiliary signal can be accomplished by a single operational amplifier, without requiring a buffer amplifier as in known noise reduction circuits. The auxiliary signal path includes a voltage-to-current converter having differential inputs and differential outputs, with a PN junction pair and at least first and second common emitter transistor pairs connected to the differential outputs. The output current of the first common emitter transistor pair is fed back to a differential input terminal of the voltage-to-current converter, and the auxiliary signal path output is derived from the second emitter common transistor pair.
摘要翻译： 噪声降低电路具有主信号路径和具有可控截止频率的高通滤波器的特性的辅助信号路径，控制电路将高通滤波器的截止频率作为 辅助信号路径输出。 导出辅助信号路径电流作为电流源输出，使得主信号和辅助信号的相加可以由单个运算放大器完成，而不需像已知的降噪电路那样使用缓冲放大器。 辅助信号路径包括具有差分输入和差分输出的电压 - 电流转换器，其具有PN结对和连接到差分输出的至少第一和第二公共发射极晶体管对。 第一公共发射极晶体管对的输出电流被反馈到电压 - 电流转换器的差分输入端，辅助信号路径输出从第二发射极公共晶体管对导出。
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公开(公告)号：US4453091A
公开(公告)日：1984-06-05
申请号：US360903
申请日：1982-03-23
CPC分类号： H03G1/0005 , H03G7/002
摘要： A level detecting circuit for use in a noise reduction circuit and which produces a level detected output signal in response to an input signal, includes an operational amplifier with at least one feedback diode for logarithmically converting the input signal to produce a logarithmically converted signal; a first PN junction element comprised of a first diode supplied with the logarithmically converted signal; a second PN junction element comprised of a second diode connected in series with the first diode at a connection point, the series-circuit of the first and second diodes having a first saturation current; a first integrating capacitor having a first capacitance and connected to the connection point for producing an integrated signal; a third PN junction element comprised of series-connected third and fourth diodes connected in parallel with the series connection of the first and second diodes and having a second saturation current greater than the first saturation current; a second integrating capacitor having a second capacitance less than the first capacitance and connected to the second and fourth diodes; a reference current source for providing a reference current to the series-connected first and second diodes and series-connected third and fourth diodes, and an output circuit for producing the level detected output signal in response to the integrated signal, such that, upon an abrupt attenuation of the input signal, the level of the level detected output signal is maintained for a predetermined time to substantially eliminate low frequency band harmonic distortion.
摘要翻译： 一种用于噪声降低电路并且响应于输入信号产生电平检测的输出信号的电平检测电路包括具有至少一个反馈二极管的运算放大器，用于对数转换输入信号以产生对数转换的信号; 第一PN结元件，由提供有对数转换信号的第一二极管组成; 第二PN结元件，包括在连接点处与所述第一二极管串联连接的第二二极管，所述第一和第二二极管的串联电路具有第一饱和电流; 第一积分电容器，具有第一电容并连接到所述连接点以产生积分信号; 第三PN结元件，包括与第一和第二二极管的串联连接并联的串联连接的第三和第二二极管，并具有大于第一饱和电流的第二饱和电流; 第二积分电容器，具有小于第一电容的第二电容并连接到第二和第四二极管; 用于向串联连接的第一和第二二极管和串联连接的第三和第四二极管提供参考电流的参考电流源，以及响应于积分信号产生电平检测的输出信号的输出电路， 输入信号的突然衰减，电平检测输出信号的电平保持预定时间，以基本上消除低频带谐波失真。
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公开(公告)号：US4441084A
公开(公告)日：1984-04-03
申请号：US300432
申请日：1981-09-08
CPC分类号： H03G9/025
摘要： A noise reduction circuit for use in an audio signal recording/reproducing apparatus is comprised of a first signal path including a voltage-controlled amplifier for amplifying a signal supplied thereto with controllable gain and integrating circuit for integrating at least that portion of the signal passing through the voltage-controlled amplifier within the audio range; a level detecting circuit for controlling the gain of the voltage-controlled amplifier in response to the level of the signal passing through the voltage-controlled amplifier; a feedforward resistor connected in parallel with the first signal path for providing a lower limit to the gain imparted to the signal supplied to the noise reduction circuit; an adder circuit for adding the output signals from the first signal path and the feedforward resistor; a second resistor or a low-pass filter connected as a negative feedback path between the output of the adder circuit and the input of the first signal path for providing an upper limit to the gain imparted to the signal supplied to the noise reduction circuit; and an anti-limiting circuit connected in parallel with the first signal path for compensating the signal supplied to the noise reduction circuit when the level of the signal is abruptly increased.
摘要翻译： 用于音频信号记录/再现装置的降噪电路包括一个第一信号路径，该第一信号路径包括用于放大其中提供的信号的可控增益的电压控制放大器和积分电路，用于至少整合通过的信号的那部分 音频范围内的压控放大器; 电平检测电路，用于响应于通过压控放大器的信号的电平来控制压控放大器的增益; 与第一信号路径并联连接的前馈电阻器，用于对被提供给降噪电路的信号赋予增益的下限; 加法电路，用于将来自第一信号路径和前馈电阻器的输出信号相加; 连接在加法器电路的输出端和第一信号路径的输入端之间作为负反馈路径的第二电阻器或低通滤波器，用于提供施加到提供给降噪电路的信号的增益的上限; 以及与第一信号路径并联连接的反限制电路，用于当信号电平突然增加时补偿提供给噪声降低电路的信号。
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公开(公告)号：US4422051A
公开(公告)日：1983-12-20
申请号：US286243
申请日：1981-07-23
申请人： Masayuki Katakura , Kenzo Akagiri
发明人： Masayuki Katakura , Kenzo Akagiri
CPC分类号： H03G3/12 , H03G1/0005 , H03G1/0023 , H03G3/02 , H03G7/002
摘要： A gain control circuit particularly suitable for compressing or expanding the dynamic range of an audio signal, and thereby reducing noise produced during recording and playback comprises an input circuit receiving an input signal, first and second differential amplifiers each supplied from the input circuit with a signal derived from the input signal, with the amplifying elements of each being complementary to the amplifying elements of the other, a first pair of transistors having their emitters coupled to the output of the first differential amplifier and a second pair of transistors having their emitters coupled to the output of the second differential amplifier. The transistors of each pair are of the same conductivity type as the amplifying elements of the associated differential amplifier. The collectors of the transistors of each pair are jointed respectively to the collectors of the corresponding transistors of the other pair. Control voltage input terminals are respectively connected to one transistor of each pair and an opposite transistor of the other pair. A feedback signal is applied from the joined collectors of the one transistors to the input circuit, and an output current is applied from the joined collectors of the other transistors to an output stage which can include a load resistor or a current-to-voltage converter circuit. This arrangement prevents variation in total static current when gain is varied, thereby achieving a superior signal-to-noise characteristic.
摘要翻译： 特别适合于压缩或扩展音频信号的动态范围并由此降低在记录和重放期间产生的噪声的增益控制电路包括接收输入信号的输入电路，每个由输入电路提供信号的第一和第二差分放大器 从所述输入信号导出，其中每个的放大元件与另一个的放大元件互补，第一对晶体管具有耦合到第一差分放大器的输出的发射极和第二对晶体管，其发射极耦合到 第二个差分放大器的输出。 每对的晶体管具有与相关联的差分放大器的放大元件相同的导电类型。 每对晶体管的集电极分别连接到另一对晶体管的集电极。 控制电压输入端子分别连接到每对的一个晶体管和另一对的相反的晶体管。 反馈信号从一个晶体管的连接的集电极施加到输入电路，并且输出电流从其他晶体管的所连接的集电极施加到输出级，输出级可以包括负载电阻器或电流 - 电压转换器 电路。 这种布置防止增益变化时总静态电流的变化，从而实现优异的信噪比特性。
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公开(公告)号：US4203043A
公开(公告)日：1980-05-13
申请号：US903246
申请日：1978-05-05
申请人： Masayuki Katakura
发明人： Masayuki Katakura
CPC分类号： H03K5/24 , G11B15/026 , H03K5/08
摘要： A switching circuit having a current source connected to first, second and third lines in order to supply first and second current signals whose total amount remains constant to the first and second current lines, respectively. The current source further supplies a constant bias I.sub.B to the third line. First and second diode pairs are respectively connected in parallel in opposite directions between the first and third signal current lines, and between the second and third signal lines, respectively. First and second transistors are connected to the three signal current lines, respectively, with the base voltages of these transistors kept constant at the same voltage level. Accordingly, current passing through the first and second diode pairs change flow direction in accordance with the incremental variations of current flowing in the first and second lines. As a result, the output voltages at the collectors of the first and second transistors represent any of the three prescribed states in accordance with the extent of the incremental current variation in the first and second lines.
摘要翻译： 一种开关电路，具有连接到第一，第二和第三线路的电流源，以分别提供总量保持恒定于第一和第二电流线的第一和第二电流信号。 电流源进一步向第三线提供恒定的偏置IB。 第一和第二二极管对分别在第一和第三信号电流线之间以及第二和第三信号线之间的相反方向上分别并联连接。 第一和第二晶体管分别连接到三条信号电流线，这些晶体管的基极电压保持恒定在相同的电压电平。 因此，通过第一和第二二极管对的电流根据在第一和第二线路中流动的电流的增量变化而改变流动方向。 结果，第一和第二晶体管的集电极处的输出电压根据第一和第二线路中增量电流变化的程度来表示三个规定状态中的任一个。
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公开(公告)号：US4109165A
公开(公告)日：1978-08-22
申请号：US768367
申请日：1977-02-14
申请人： Masayuki Katakura , Hisashi Yamada
发明人： Masayuki Katakura , Hisashi Yamada
摘要： An RMS circuit comprising a logarithmic amplifying circuit, a fullwave rectifying circuit for subjecting an output from the logarithmic amplifying circuit to fullwave rectification, and a smoothing circuit for smoothing an output signal from the fullwave rectifying circuit, wherein the logarithmic amplifying circuit is provided with an operational amplifier whose noninverting input terminal is grounded and whose inverting input terminal is connected to a signal source; a first npn transistor whose collector is connected to the inverting input terminal of the operational amplifier and whose base is grounded; a first diode whose anode is connected to the emitter of the first npn transistor and whose cathode is connected to the output terminal of the operational amplifier; a second diode whose anode is connected to the output terminal of the operational amplifier; and a third diode whose anode is connected to the cathode of the second diode and whose cathode is connected to the noninverting input terminal of the operational amplifier.
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公开(公告)号：US07619473B2
公开(公告)日：2009-11-17
申请号：US11812378
申请日：2007-06-18
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45475 , H03F3/45659 , H03F3/45748 , H03F3/45757 , H03F3/45973 , H03F3/45982 , H03F2200/513 , H03F2203/45082 , H03F2203/45088 , H03F2203/45134 , H03F2203/45212 , H03F2203/45526 , H03F2203/45644
摘要： A fully-differential amplifier able to operate at a low power supply voltage and provided with a common-mode signal suppression function is disclosed. This fully-differential amplifier is provided with a first fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the input side by a feedforward means and a second fully-differential amplifier configured by a single-stage configuration inverting amplifier and canceling out the common-mode signal of the output side by a feedback means, the output of the first fully-differential amplifier being connected to the input of the second fully-differential amplifier.
摘要翻译： 公开了能够在低电源电压下工作并提供共模信号抑制功能的全差分放大器。 该全差分放大器配备有由单级配置反相放大器配置的第一全差分放大器，并且由前馈装置消除输入侧的共模信号，并且由单个配置反相放大器配置的第二全差分放大器 级配置反相放大器，并通过反馈装置消除输出侧的共模信号，第一全差分放大器的输出连接到第二全差分放大器的输入端。
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公开(公告)号：US20050195014A1
公开(公告)日：2005-09-08
申请号：US11049784
申请日：2005-02-03
申请人： Masayuki Katakura
发明人： Masayuki Katakura
CPC分类号： G06G7/16 , H03B19/00 , H03D7/1458 , H03D7/1466 , H03D7/1483 , H03D2200/0086
摘要： A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.
摘要翻译： 正弦波乘法电路将模拟输入信号乘以每个具有唯一值的n（n是等于或大于2的整数）加权系数。 模拟输入信号乘以n个加权系数中的一个的极性被改变。 此外，n个加权系数和极性之间的切换在正弦的一个周期的等于½k（k是整数，2k等于或大于6但等于或小于4n）的每个采样周期之后执行 波信号，模拟输入信号通过该信号相乘。 结果，产生具有2n个正和负楼梯的阶梯波形，同时可以减少模拟输入信号相乘的正弦波信号附近的不必要的谐波分量。
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公开(公告)号：US06798300B2
公开(公告)日：2004-09-28
申请号：US10374502
申请日：2003-02-25
IPC分类号： H03B520
CPC分类号： H03C3/095 , H03C3/0958 , H03K3/0315 , H03L7/0995 , H03L7/18
摘要： An oscillator having a modulation function capable of controlling a frequency by adding a signal to a control signal and a PLL circuit using the same, wherein the oscillator forms a ring comprised of a plurality of cascade connected delay stages controlled in delay value by an inverter or a buffer and a control signal and forming a closed loop by an inverted phase and comprises a modulation function modulating an oscillation frequency by adding a modulation signal to the control signal in a part of the plurality of delay stages.
摘要翻译： 具有调制功能的振荡器，其能够通过向控制信号添加信号来控制频率，并且使用该振荡器形成由逆变器控制在延迟值中的多个级联连接的延迟级的环， 缓冲器和控制信号，并且通过反相形成闭环，并且包括通过在多个延迟级的一部分中对控制信号添加调制信号来调制振荡频率的调制函数。
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