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    Semiconductor integrated circuit device
    13.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US20060291110A1

    公开(公告)日：2006-12-28

    申请号：US11447168

    申请日：2006-06-06

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Yoshihiko Yasu ,  Kenji Hirose ,  Takahiro Irita

    IPC分类号： H02H7/00

    CPC分类号： H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated. A layout may be provided in a direction vertical to a direction in which cells are arranged in a row direction for the purpose of dispersing a current of a light supply line.

    摘要翻译： 提供了一种半导体集成电路器件，该电路能够布置控制信号系统，避免不能检查不确定的信号传播防止电路等的危险，进一步便于针对安装在自动化工具上的检查，并且促进 功率关断控制芯片内部。 在半导体集成电路装置中，功率关闭优先级由独立的电源区域A至区域I提供。规定了在具有高优先级的电路被接通的情况下，规定了具有 其较低优先级不能关闭，从而有助于设计方法。 此外，在独立电源区域A至区域I中提供能够应用另一电源的区域。在该区域中，集成了用于保存信息的中继缓冲器（中继器）和时钟缓冲器或信息保持锁存器。 为了分散供电线的电流，布置可以沿垂直于单元布置在行方向上的方向设置。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    14.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20090079465A1

    公开(公告)日：2009-03-26

    申请号：US11912272

    申请日：2005-04-21

    申请人： Toshio Sasaki ,  Yoshihiko Yasu ,  Ryo Mori ,  Koichiro Ishibashi ,  Yusuke Kanno

    发明人： Toshio Sasaki ,  Yoshihiko Yasu ,  Ryo Mori ,  Koichiro Ishibashi ,  Yusuke Kanno

    IPC分类号： H03K17/16

    CPC分类号： H01L27/0207 ,  H01L27/11803

    摘要： The present invention aims to make each power shutdown area appropriate.Cell areas each comprising a plurality of core cells arranged therein, and power switches disposed corresponding to the respective cell areas are provided. A plurality of power shutdown areas are respectively formed in units of the core cells. In each power shutdown area, power shutdown is enabled by the power switches corresponding to the power shutdown areas. Thus, the power shutdown areas can be set finely in the core cell units, and the appropriateness of each power shutdown area is achieved. With its appropriateness, a reduction in current consumption at standby is achieved.

    摘要翻译： 本发明旨在使每个功率关闭区域适合。 提供了各自包括布置在其中的多个核心单元的单元区域，以及对应于各个单元区域布置的功率开关。 多个功率关闭区分别以核心单元为单位形成。 在每个电源关闭区域，通过与电源关闭区域对应的电源开关使能电源关闭。 因此，可以在核心单元单元中精细地设置功率关闭区域，并且实现每个功率关闭区域的适当性。 在适当的情况下，实现了待机状态下电流消耗的减少。

    Semiconductor integrated circuit and data processing system
    16.
    发明授权
    Semiconductor integrated circuit and data processing system 有权
    半导体集成电路和数据处理系统

    公开(公告)号：US07254680B2

    公开(公告)日：2007-08-07

    申请号：US11641808

    申请日：2006-12-20

    申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

    发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

    IPC分类号： G06F12/00 ,  G11C7/00

    CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

    摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

    摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

    Semiconductor integrated circuit and data processing system
    17.
    发明授权
    Semiconductor integrated circuit and data processing system 有权
    半导体集成电路和数据处理系统

    公开(公告)号：US06381671B1

    公开(公告)日：2002-04-30

    申请号：US09342240

    申请日：1999-06-29

    申请人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

    发明人： Kazushige Ayukawa ,  Seiji Miura ,  Jun Satoh ,  Takao Watanabe ,  Kazumasa Yanagisawa ,  Yusuke Kanno ,  Hiroyuki Mizuno

    IPC分类号： G06F1200

    CPC分类号： G11C7/1006 ,  G06F12/0215 ,  G06F12/0893 ,  G06F13/161 ,  G06F2212/3042 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4093 ,  G11C2207/104 ,  G11C2207/2245

    摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

    摘要翻译： 为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。 数据保存在每个存储体的读出放大器中。 当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。 即，使每个存储体用作读出放大器高速缓存。 为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据 地址由另一个存储体中的读出放大器预读。

    Semiconductor device
    18.
    发明申请
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US20050285659A1

    公开(公告)日：2005-12-29

    申请号：US11202279

    申请日：2005-08-12

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

    IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088 ,  H03K3/356 ,  H03K5/1534 ,  H03K19/0175 ,  H03K19/0185

    CPC分类号： H03K5/1534 ,  H03K3/356113 ,  H03K19/018521

    摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

    摘要翻译： 半导体器件包括差分电平转换器电路，其接收第一信号并输出​​更大振幅的第二信号。 差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。 使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。 即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

    Semiconductor device
    19.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US07375574B2

    公开(公告)日：2008-05-20

    申请号：US11202279

    申请日：2005-08-12

    申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

    发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

    IPC分类号： H03L5/00

    CPC分类号： H03K5/1534 ,  H03K3/356113 ,  H03K19/018521

    摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

    摘要翻译： 半导体器件包括差分电平转换器电路，其接收第一信号并输出​​更大振幅的第二信号。 差分电平转换器具有用于接收第一信号的第一MISFET对，用于增强第一MISFET对的耐受电压的第二MISFET对以及具有用于锁存来自输出的第二信号的交叉耦合门的第三MISFET对。 使第二MISFET对和第三MISFET对的栅极绝缘膜的膜厚比第一MISFET对的膜厚薄，并且使第一MISFET对和第二MISFET对的阈值电压小于第三MISFET对的阈值电压。 即使在电平转换之前和之后的信号幅度有较大的差异，该电平转换器电路也以高速工作。

    Semiconductor integrated circuit device
    20.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07230477B2

    公开(公告)日：2007-06-12

    申请号：US11296442

    申请日：2005-12-08

    申请人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yohihiko Yasu ,  Nobuhiro Oodaira

    发明人： Hiroyuki Mizuno ,  Yusuke Kanno ,  Kazumasa Yanagisawa ,  Yohihiko Yasu ,  Nobuhiro Oodaira

    IPC分类号： H01L2/00

    CPC分类号： H03K19/0016 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0928 ,  H01L27/11898 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.

    摘要翻译： 具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。 第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。 转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。 转换电路（MIO 1〜MIO 4）通常用于连接电路块。