公开(公告)号：US06438722B1

公开(公告)日：2002-08-20

申请号：US09372697

申请日：1999-08-11

申请人： Roger Ned Bailey ,  Michael Stephen Floyd ,  Bradley McCredie ,  Kevin Franklin Reick ,  Hugh Rodney Stigdon ,  Jennifer Lane Vargus

发明人： Roger Ned Bailey ,  Michael Stephen Floyd ,  Bradley McCredie ,  Kevin Franklin Reick ,  Hugh Rodney Stigdon ,  Jennifer Lane Vargus

IPC分类号： G01R3128

CPC分类号： G06F11/27 ,  G01R31/319

摘要： The foregoing objects are achieved as is now described. A method and system for testing an integrated circuit are provided. A test substrate is provided which is manufactured by the same particular production technology for which the complex integrated circuit is designed. A pattern generator for generating test data and a result checker for comparing output data are embedded on the test substrate. Isolated portions of circuitry of the integrated circuit are selectively embedded onto the test substrate. The isolated portions of circuitry are subjected to testing by applying test data from the pattern generator to the isolated portions of circuitry. Errors in the isolated portions of circuitry are detected with the result checker by comparing data output from the isolated portions of circuitry with predetermined expected data, such that the integrated circuit is tested by susets, independently of testing the integrated circuit in its entirety.

摘要翻译： 如上所述实现上述目的。 提供了一种用于测试集成电路的方法和系统。 提供了由设计复合集成电路的相同特定生产技术制造的测试基板。 用于产生测试数据的图形发生器和用于比较输出数据的结果检查器嵌入在测试基板上。 集成电路的电路的隔离部分选择性地嵌入到测试基板上。 通过将来自图案发生器的测试数据应用到电路的隔离部分来对电路的隔离部分进行测试。 通过将来自电路的隔离部分的输出的数据与预定的预期数据进行比较来检测电路的隔离部分中的错误，使得集成电路被检测到，而不考虑集成电路的整体。

公开(公告)号：US07080288B2

公开(公告)日：2006-07-18

申请号：US10425423

申请日：2003-04-28

申请人： Frank David Ferraiolo ,  Michael Stephen Floyd ,  Robert James Reese ,  Kevin Franklin Reick

发明人： Frank David Ferraiolo ,  Michael Stephen Floyd ,  Robert James Reese ,  Kevin Franklin Reick

IPC分类号： G06F11/22

CPC分类号： H04L43/50 ,  G06F11/221 ,  H04L1/00 ,  H04L1/242

摘要： A method an apparatus for interface failure survivability using error correction provides operation of an interface when a number of bits of the interface less than or equal to available error correction depth are present. Initialization tests are used to determine whether the interface errors due to failed interconnects or circuits can be corrected, or whether the interface must be disabled. Subsequent alignment at initialization or during operation idle periods may be disabled for any failed bit paths. The failed bit path indications are determined and maintained in hardware, and used to bypass subsequent calibrations that could otherwise corrupt the interface. A fault indication specifying total failure may be generated and used to shut down the interface and/or connected subsystem in response to an uncorrectable condition and request immediate repair. A second fault indication specifying correctable failure may be generated and used to indicate a need for eventual repair.

摘要翻译： 一种使用错误校正的接口故障生存性的装置的方法提供当接口的位数小于或等于可用纠错深度时的接口的操作。 初始化测试用于确定由于互连或电路故障导致的接口错误是否可以更正，还是禁用接口。 对于任何故障的位路径，在初始化或操作空闲期间的后续对齐可被禁用。 失败的位路径指示被确定并维护在硬件中，并用于绕过可能会破坏接口的后续校准。 可以产生指示全部故障的故障指示并用于响应于不可校正的状况而关闭接口和/或连接的子系统并请求立即修复。 可以产生指示可修正故障的第二故障指示并用于指示最终修复的需要。

公开(公告)号：US20080141000A1

公开(公告)日：2008-06-12

申请号：US12033385

申请日：2008-02-19

申请人： Michael Stephen Floyd ,  Larry Scott Leitner

发明人： Michael Stephen Floyd ,  Larry Scott Leitner

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

公开(公告)号：US07343476B2

公开(公告)日：2008-03-11

申请号：US11055044

申请日：2005-02-10

申请人： Michael Stephen Floyd ,  Larry Scott Leitner

发明人： Michael Stephen Floyd ,  Larry Scott Leitner

IPC分类号： G06F9/30

CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3842 ,  G06F9/3867 ,  G06F11/0715 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/1407

摘要： Monitoring is performed to detect a hang condition. A timer is set to detect a hang based on a core hang limit. If a thread hangs for the duration of the core hang limit, then a core hang is detected. If the thread is performing an external memory transaction, then the timer is increased to a longer memory hang limit. If the thread is waiting for a shared resource, then the timer may be increased to the longer memory hang limit if another thread or, more particularly, the thread blocking the resource has a pending memory transaction. Responsive to detecting a hang condition, instructions dispatched to the plurality of execution units may be flushed, or the processor may be reset and restored to a previously known good, checkpointed architected state.

摘要翻译： 执行监视以检测挂起状况。 一个定时器被设置为基于核心挂起限制来检测挂起。 如果线程在核心挂起限制的持续时间内挂起，则会检测到核心挂起。 如果线程正在执行外部存储器事务，则定时器增加到更长的内存挂起限制。 如果线程正在等待共享资源，则如果另一个线程，更具体地说，阻塞资源的线程具有未决的存储器事务，则定时器可​​能会增加到更长的内存挂起限制。 响应于检测挂起状况，可以刷新发送到多个执行单元的指令，或者可以将处理器复位并恢复到先前已知的良好的，检查点的架构状态。

公开(公告)号：US06633838B1

公开(公告)日：2003-10-14

申请号：US09435071

申请日：1999-11-04

申请人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

发明人： Lakshminarayana Baba Arimilli ,  Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick ,  Jennifer Lane Vargus

IPC分类号： G06F1125

CPC分类号： G06F11/2236

摘要： The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis. Trace array input and output logic allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. Further, the trace array input and output logic is preferably accessible at both the wafer and component stage to allow for testing and debugging of the VLSI circuitry.

摘要翻译： 本发明的系统和方法体现在优选集成到VLSI电路中的多状态片上逻辑分析仪中。 通常，逻辑分析器优选地耦合到多级跟踪阵列，用于存储由逻辑分析器生成的事件跟踪数据。 耦合到跟踪阵列和逻辑分析仪的输入和输出逻辑器允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 逻辑分析仪具有匹配一个或多个可编程触发事件的能力，以满足一个或多个可编程条件。 此外，逻辑分析器优选地具有在期望状态下初始化可编程条件的能力，并且将事件跟踪数据存储在用于跟踪数据重建和分析的片上阵列中。 跟踪数组输入和输出逻辑允许从跟踪数组读取或写入数据，以及对逻辑分析器内的转换状态的触发和条件标准进行编程。 此外，迹线阵列输入和输出逻辑优选在晶片和元件级可访问以允许对VLSI电路进行测试和调试。

公开(公告)号：US20120216210A1

公开(公告)日：2012-08-23

申请号：US13459398

申请日：2012-04-30

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/50

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派的事件来确定相对资源的使用，其可以包括仍然占据处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US08209698B2

公开(公告)日：2012-06-26

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F7/38

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US20100037233A1

公开(公告)日：2010-02-11

申请号：US12579540

申请日：2009-10-15

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。

公开(公告)号：US06802031B2

公开(公告)日：2004-10-05

申请号：US09864114

申请日：2001-05-24

申请人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick

发明人： Michael Stephen Floyd ,  Larry Scott Leitner ,  Kevin F. Reick

IPC分类号： G06F1100

CPC分类号： G06F11/366 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/3636 ,  G06F2201/835 ,  G06F2201/86 ,  G06F2201/88

摘要： A trace array for recording states of signals includes N-storage locations for k trace signals. In the write mode, an address generator combines the outputs of an event signal counter and a cycle clock counter to generate trace array addresses. A start code is written each time an event signal occurs and event addresses are saved. Recording is stopped by a stop signal and the stop address is saved. A compression code and time stamp code are written when no state changes occur in any trace signals at the cycle clock times to compress recorded trace signal data. An output processor reads out stored states of the trace signals and uses the start codes, event addresses, stop address, compression code and time stamp to reconstruct the original trace signal sequences for analysis.

摘要翻译： 用于记录信号状态的迹线阵列包括用于k个跟踪信号的N个存储位置。 在写模式下，地址生成器将事件信号计数器和周期时钟计数器的输出相结合，生成跟踪数组地址。 每次发生事件信号时写入起始码，并保存事件地址。 通过停止信号停止录像，并保存停止地址。 当在周期时钟时间的任何跟踪信号中没有状态变化时，压缩码和时间戳码被写入，以压缩记录的跟踪信号数据。 输出处理器读出跟踪信号的存储状态，并使用起始码，事件地址，停止地址，压缩码和时间戳重建原始跟踪信号序列进行分析。

公开(公告)号：US09003417B2

公开(公告)日：2015-04-07

申请号：US13459398

申请日：2012-04-30

申请人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

发明人： William Joseph Armstrong ,  Michael Stephen Floyd ,  Ronald Nick Kalla ,  Larry Scott Leitner ,  Balaram Sinharoy

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F9/38 ,  G06F9/50 ,  G06F11/34

CPC分类号： G06F9/3851 ,  G06F9/50 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/88 ,  G06F2201/885

摘要： Processor time accounting is enhanced by per-thread internal resource usage counter circuits that account for usage of processor core resources to the threads that use them. Relative resource use can be determined by detecting events such as instruction dispatches for multiple threads active within the processor, which may include idle threads that are still occupying processor resources. The values of the resource usage counters are used periodically to determine relative usage of the processor core by the multiple threads. If all of the events are for a single thread during a given period, the processor time is allocated to the single thread. If no events occur in the given period, then the processor time can be equally allocated among threads. If multiple threads are generating events, a fractional resource usage can be determined for each thread and the counters may be updated in accordance with their fractional usage.

摘要翻译： 处理器时间计费通过每线程内部资源使用计数器电路来增强，这些计算器电路考虑到使用它们的线程使用处理器核心资源。 可以通过检测诸如在处理器内活动的多个线程的指令分派等事件来确定相对资源的使用，这可能包括仍占用处理器资源的空闲线程。 周期性地使用资源使用计数器的值来确定多个线程对处理器核心的相对使用。 如果所有事件在给定时间段内都是针对单个线程，则处理器时间被分配给单个线程。 如果在给定的时间段内没有发生任何事件，那么处理器的时间可以在线程之间平均分配。 如果多个线程正在生成事件，则可以为每个线程确定分数资源使用，并且可以根据其分数使用来更新计数器。