公开(公告)号：US07851891B2

公开(公告)日：2010-12-14

申请号：US12424894

申请日：2009-04-16

申请人： Naohisa Sengoku ,  Michikazu Matsumoto

发明人： Naohisa Sengoku ,  Michikazu Matsumoto

IPC分类号： H01L29/06

CPC分类号： H01L27/0629

摘要： A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一绝缘膜; 去除所述第一绝缘膜的一部分; 在所述半导体衬底上去除了所述第一绝缘膜的所述部分的区域上形成漏电流密度高于所述第一绝缘膜的漏电流密度的第二绝缘膜; 在第一和第二绝缘膜上形成未掺杂的半导体膜; 将杂质注入未掺杂的半导体膜的一部分中，从而限定第一导电类型的半导体区域作为离散岛点缀; 在第一导电类型的半导体区域和未掺杂的半导体膜上形成第三绝缘膜; 并通过湿蚀刻去除第三绝缘膜的一部分。 至少第二绝缘膜形成在第一导电类型的半导体区域下方。

公开(公告)号：US20090206454A1

公开(公告)日：2009-08-20

申请号：US12424894

申请日：2009-04-16

申请人： Naohisa SENGOKU ,  Michikazu Matsumoto

发明人： Naohisa SENGOKU ,  Michikazu Matsumoto

IPC分类号： H01L29/06

CPC分类号： H01L27/0629

摘要： A method for fabricating a semiconductor device includes the steps of: forming a first insulating film on a semiconductor substrate; removing part of the first insulating film; forming a second insulating film having a leakage current density higher than that of the first insulating film on a region where the part of the first insulating film has been removed on the semiconductor substrate; forming an undoped semiconductor film on the first and second insulating films; implanting an impurity into part of the undoped semiconductor film, thereby defining semiconductor regions of a first conductivity type dotted as discrete islands; forming a third insulating film on the semiconductor regions of the first conductivity type and the undoped semiconductor film; and removing part of the third insulating film by wet etching. At least the second insulating film is formed under the semiconductor regions of the first conductivity type.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一绝缘膜; 去除所述第一绝缘膜的一部分; 在所述半导体衬底上去除了所述第一绝缘膜的所述部分的区域上形成漏电流密度高于所述第一绝缘膜的漏电流密度的第二绝缘膜; 在第一和第二绝缘膜上形成未掺杂的半导体膜; 将杂质注入未掺杂的半导体膜的一部分中，从而限定第一导电类型的半导体区域作为离散岛点缀; 在第一导电类型的半导体区域和未掺杂的半导体膜上形成第三绝缘膜; 并通过湿蚀刻去除第三绝缘膜的一部分。 至少第二绝缘膜形成在第一导电类型的半导体区域下方。

公开(公告)号：US07126174B2

公开(公告)日：2006-10-24

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L29/76

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

公开(公告)号：US06720241B2

公开(公告)日：2004-04-13

申请号：US10172750

申请日：2002-06-17

申请人： Michikazu Matsumoto ,  Naohisa Sengoku ,  Ayumi Kobayashi

发明人： Michikazu Matsumoto ,  Naohisa Sengoku ,  Ayumi Kobayashi

IPC分类号： H01L21265

CPC分类号： H01L21/823418 ,  H01L21/823437 ,  H01L21/823481

摘要： In a method for manufacturing a semiconductor device, impurity ion is implanted into a semiconductor layer so as to form an ion implantation region in the semiconductor layer, and at least the ion implantation region is turned amorphous. Then, an insulating film is formed on the semiconductor layer at a temperature at which the ion implantation region is not crystallized, and then the semiconductor layer is annealed in a non-oxidizing atmosphere so as to activate the impurity ion implanted into the semiconductor layer.

摘要翻译： 在半导体器件的制造方法中，将杂质离子注入到半导体层中，以在半导体层中形成离子注入区域，并且至少离子注入区域变为无定形。 然后，在离子注入区域未结晶的温度下，在半导体层上形成绝缘膜，然后在非氧化性气氛中对半导体层进行退火，以激活注入到半导体层中的杂质离子。

公开(公告)号：US6100170A

公开(公告)日：2000-08-08

申请号：US110942

申请日：1998-07-07

申请人： Michikazu Matsumoto ,  Tatsuo Sugiyama ,  Shinichi Ogawa ,  Masato Kanazawa ,  Kouji Tamura ,  Masahiro Yasumi

发明人： Michikazu Matsumoto ,  Tatsuo Sugiyama ,  Shinichi Ogawa ,  Masato Kanazawa ,  Kouji Tamura ,  Masahiro Yasumi

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/425 ,  H01L21/3205

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28512 ,  H01L21/28518

摘要： After forming a polysilicon film to be used as a gate electrode on a semiconductor substrate of silicon, an insulating thin film is deposited on the polysilicon film. Impurity ions are implanted into the polysilicon film through the insulating thin film, so as to form an amorphous layer on the surface of the polysilicon film. After removing the insulating thin film existing on the polysilicon film, a metal film is deposited on the amorphous layer. A reaction is caused between the amorphous layer and the metal film through annealing, so as to form a metal silicide layer on the surface of the polysilicon film.

摘要翻译： 在硅的半导体衬底上形成用作栅电极的多晶硅膜之后，在多晶硅膜上沉积绝缘薄膜。 通过绝缘薄膜将杂质离子注入到多晶硅膜中，以在多晶硅膜的表面上形成非晶层。 在去除存在于多晶硅膜上的绝缘薄膜之后，在非晶层上沉积金属膜。 通过退火在非晶层与金属膜之间产生反应，从而在多晶硅膜的表面上形成金属硅化物层。

公开(公告)号：US5726479A

公开(公告)日：1998-03-10

申请号：US584123

申请日：1996-01-11

申请人： Michikazu Matsumoto ,  Minoru Fujii ,  Toshiki Yabu

发明人： Michikazu Matsumoto ,  Minoru Fujii ,  Toshiki Yabu

IPC分类号： H01L23/532 ,  H01L29/49 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/4933 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： A polysilicon electrode is formed in an active area surrounded by an isolation on a silicon substrate with a gate oxide film sandwiched therebetween, a polysilicon wire is formed on the isolation, and a source/drain region is formed on both sides of the polysilicon electrode. On the both sides of a polysilicon film constituting the electrode and the wire are formed side walls having a height that is 4/5 or less of the height of the polysilicon film. Furthermore, the polysilicon film is provided with a silicide layer in contact with the top surface and portions of the side surfaces of the polysilicon film projecting from the side walls, and another silicide layer is formed in contact with the source/drain region. Since the sectional area of the silicide layer is increased, the resistance value can be suppressed even when the dimension of the polysilicon film is minimized. Thus, the invention provides a semiconductor device including an FET having a low resistance value applicable to a refined pattern.

摘要翻译： 在由硅衬底上的隔离包围的有源区域中形成多晶硅电极，其间夹有栅极氧化膜，在隔离层上形成多晶硅导线，并在多晶硅电极的两侧形成源极/漏极区域。 在构成电极和导线的多晶硅膜的两侧形成高度为多晶硅膜的高度为+ E，fra 4/5 + EE以下的侧壁。 此外，多晶硅膜设置有与侧壁突出的顶表面和多晶硅膜的侧表面的部分接触的硅化物层，并且另外的硅化物层形成为与源极/漏极区域接触。 由于硅化物层的截面积增加，所以即使当多晶硅膜的尺寸最小化时也可以抑制电阻值。 因此，本发明提供一种包括具有适用于精细图案的低电阻值的FET的半导体器件。

公开(公告)号：US20050093089A1

公开(公告)日：2005-05-05

申请号：US10995283

申请日：2004-11-24

申请人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

发明人： Mizuki Segawa ,  Isao Miyanaga ,  Toshiki Yabu ,  Takashi Nakabayashi ,  Takashi Uehara ,  Kyoji Yamashita ,  Takaaki Ukeda ,  Masatoshi Arai ,  Takayuki Yamada ,  Michikazu Matsumoto

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L29/00

CPC分类号： H01L29/6659 ,  H01L21/76224 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

摘要： An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area. In this manner, the integration of a semiconductor device can be improved and an area occupied by the semiconductor device can be decreased without causing degradation of junction voltage resistance and increase of a junction leakage current in the semiconductor device.

摘要翻译： 形成了比硅衬底的有源区域更高级的隔离。 在有源区域上，形成包括栅极氧化膜，栅电极，栅极保护膜，侧壁等的FET。 绝缘膜沉积在基板的整个顶表面上，并且在绝缘膜上形成用于暴露在有源区上延伸的区域，一部分隔离栅极保护膜的抗蚀剂膜。 不需要提供用于避免与形成连接孔的区域的隔离等的干涉的取向余量。 由于隔离比有源区域以逐步方式更高，所以通过在形成连接孔中的过度蚀刻来防止隔离物与有源区域中杂质浓度低的部分接触。 以这种方式，可以改善半导体器件的集成，并且可以降低半导体器件占据的面积，而不会导致半导体器件中的结电阻的劣化和结漏电流的增加。

公开(公告)号：US06509254B1

公开(公告)日：2003-01-21

申请号：US09680053

申请日：2000-10-05

申请人： Michikazu Matsumoto ,  Naohisa Sengoku

发明人： Michikazu Matsumoto ,  Naohisa Sengoku

IPC分类号： H01L213205

CPC分类号： H01L29/4941 ,  H01L21/28061

摘要： After depositing a first metal film of a first metal on a silicon-containing film including silicon as a main component, a second metal film of a nitride of a second metal is deposited on the first metal film. Then, a high-melting-point metal film is deposited on the second metal film, so as to form an electrode structure including the silicon-containing film, the first metal film, the second metal film and the high-melting-point metal film. The electrode structure is then subjected to a heat treatment at 750° C. or more. The first metal film has such a thickness that the first metal is nitrided to be changed into a nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film after the heat treatment.

摘要翻译： 在以包含硅为主要成分的含硅膜上沉积第一金属的第一金属膜之后，在第一金属膜上沉积第二金属的氮化物的第二金属膜。 然后，在第二金属膜上沉积高熔点金属膜，形成包含含硅膜，第一金属膜，第二金属膜和高熔点金属膜的电极结构 。 然后将电极结构在750℃以上进行热处理。 第一金属膜的厚度使得第一金属被氮化以变为第一金属的氮化物，并且在热处理后，在含硅膜的表面部分中不形成第一金属的硅化物层。

公开(公告)号：US06451690B1

公开(公告)日：2002-09-17

申请号：US09679617

申请日：2000-10-05

申请人： Michikazu Matsumoto ,  Naohisa Sengoku

发明人： Michikazu Matsumoto ,  Naohisa Sengoku

IPC分类号： H01L2144

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/2855

摘要： After forming a barrier film on a silicon-containing film including silicon as a main component, a high-melting-point metal film is deposited on the barrier film, so as to form a laminated structure including the silicon-containing film, the barrier film and the high-melting-point metal film. The laminated structure is subjected to a heat treatment at a temperature of 750° C. or more. The barrier film is formed by forming a first metal film of a nitride of a metal on the silicon-containing film; forming, on the first metal film, a second metal film of the metal or the nitride of the metal with a smaller nitrogen content than the first metal film; and forming, on the second metal film, a third metal film of the nitride of the metal with a larger nitrogen content than the second metal film.

摘要翻译： 在以硅为主要成分的含硅膜上形成阻挡膜之后，在阻挡膜上沉积高熔点金属膜，形成包含含硅膜，阻挡膜 和高熔点金属膜。 层压结构体在750℃以上的温度下进行热处理。 阻挡膜通过在含硅膜上形成金属氮化物的第一金属膜而形成; 在所述第一金属膜上形成所述金属的第二金属膜或所述金属氮化物的氮含量低于所述第一金属膜的金属膜; 以及在所述第二金属膜上形成氮化物的氮化物的第三金属膜与所述第二金属膜相比形成。

公开(公告)号：US5382544A

公开(公告)日：1995-01-17

申请号：US66882

申请日：1993-05-25

申请人： Michikazu Matsumoto ,  Kazuhiko Hashimoto

发明人： Michikazu Matsumoto ,  Kazuhiko Hashimoto

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/283 ,  H01L21/3205

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  Y10S148/017 ,  Y10S148/105 ,  Y10S438/91 ,  Y10S438/945 ,  Y10S438/949 ,  Y10S438/95

摘要： A semiconductor device is manufactured using the electron beam exposure method. A resist is applied on an interlayer dielectric film through a thin metal film, and a contact hole is formed in the interlayer dielectric film. The thin metal film is utilized as a part of a second metal wiring pattern after removing its surface oxides.

摘要翻译： 使用电子束曝光方法制造半导体器件。 通过薄金属膜将抗蚀剂施加在层间电介质膜上，并且在层间绝缘膜中形成接触孔。 在去除其表面氧化物之后，将金属薄膜用作第二金属布线图案的一部分。