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    Configurable Mailbox Data Buffer Apparatus
    12.
    发明申请
    Configurable Mailbox Data Buffer Apparatus 审中-公开
    可配置邮箱数据缓冲设备

    公开(公告)号：US20160371200A1

    公开(公告)日：2016-12-22

    申请号：US15184789

    申请日：2016-06-16

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris

    IPC: G06F13/10 ,  G06F13/20 ,  G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/102 ,  G06F13/16 ,  G06F13/20 ,  G06F13/42 ,  G06F15/167

    Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

    Abstract translation: 单片微控制器具有主核和至少一个从核。 主核心由主系统时钟计时，从核心由从系统时钟计时，并且其中每个核心分别与多个外围设备相关联以形成主微控制器和从微控制器。 在主微控制器和从属微控制器之间提供通信接口，其中通信接口具有多个可配置方向性数据寄存器，与流控制逻辑耦合，流控制逻辑可配置为向多个可配置数据寄存器中的每一个分配方向。

    Central Processing Unit With Enhanced Instruction Set
    13.
    发明申请
    Central Processing Unit With Enhanced Instruction Set 审中-公开
    具有增强指令集的中央处理单元

    公开(公告)号：US20160321202A1

    公开(公告)日：2016-11-03

    申请号：US15141823

    申请日：2016-04-29

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Bryan Kris ,  Calum Wilkie ,  Jason Sachs ,  Andreas Reiter

    IPC: G06F13/16 ,  G06F13/40 ,  G06F12/14

    CPC classification number: G06F13/1673 ,  G06F9/30043 ,  G06F9/3877 ,  G06F9/3879 ,  G06F12/14 ,  G06F13/4068 ,  G06F2212/1052

    Abstract: An integrated circuit has a master processing core with a central processing unit coupled with a non-volatile memory and a slave processing core operating independently from the master processing core and having a central processing unit coupled with volatile program memory, wherein the master central processing unit is configured to transfer program instructions into the non-volatile memory of the slave processing core and wherein a transfer of the program instructions is performed by executing a dedicated instruction within the central processing unit of the master processing core.

    Abstract translation: 集成电路具有主处理核心，其具有与非易失性存储器耦合的中央处理单元和独立于主处理核心并具有与易失性程序存储器耦合的中央处理单元操作的从属处理核心，其中主中央处理单元 被配置为将程序指令传送到从处理核心的非易失性存储器，并且其中通过在主处理核心的中央处理单元内执行专用指令来执行程序指令的传送。

    Multibit shift instruction
    14.
    发明授权
    Multibit shift instruction 有权

    公开(公告)号：US12093688B2

    公开(公告)日：2024-09-17

    申请号：US17989067

    申请日：2022-11-17

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

    IPC: G06F9/30

    CPC classification number: G06F9/30032 ,  G06F9/30123

    Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

    SYSTEMS AND METHODS FOR MANAGING INTERRUPT PRIORITY LEVELS
    16.
    发明公开
    SYSTEMS AND METHODS FOR MANAGING INTERRUPT PRIORITY LEVELS 审中-公开

    公开(公告)号：US20230176898A1

    公开(公告)日：2023-06-08

    申请号：US18073075

    申请日：2022-12-01

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  Howard Schlunder ,  David Mickey

    IPC: G06F9/48 ,  G06F8/71

    CPC classification number: G06F9/4831 ,  G06F8/71

    Abstract: A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.

    MULTIBIT SHIFT INSTRUCTION
    17.
    发明公开
    MULTIBIT SHIFT INSTRUCTION 审中-公开

    公开(公告)号：US20230176867A1

    公开(公告)日：2023-06-08

    申请号：US17989067

    申请日：2022-11-17

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey ,  Ashish Desai ,  Jason Sachs ,  Calum Wilkie

    IPC: G06F9/30

    CPC classification number: G06F9/30032

    Abstract: An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

    Central processing unit with DSP engine and enhanced context switch capabilities
    18.
    发明授权
    Central processing unit with DSP engine and enhanced context switch capabilities 有权

    公开(公告)号：US10802866B2

    公开(公告)日：2020-10-13

    申请号：US15141817

    申请日：2016-04-28

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Catherwood ,  David Mickey

    IPC: G06F9/46 ,  G06F9/30 ,  G06F9/4401

    Abstract: An integrated circuit device has a first central processing unit including a digital signal processing (DSP) engine, and a plurality of contexts, each context having a CPU context with a plurality of registers and a DSP context, wherein the DSP context has control bits and a plurality of DSP registers, wherein after a reset of the integrated circuit device the control bits of all DSP context are linked together such that data written to the control bits of a DSP context is written to respective control bits of all other DSP contexts and only after a context switch to another context and a modification of at least one of the control bits of the another DSP context, the control bits of the another context is severed from the link to form independent control bits of the DSP context.

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