公开(公告)号：US10896886B2

公开(公告)日：2021-01-19

申请号：US16276533

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US10403618B2

公开(公告)日：2019-09-03

申请号：US15711937

申请日：2017-09-21

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

公开(公告)号：US10002840B1

公开(公告)日：2018-06-19

申请号：US15672006

申请日：2017-08-08

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01074

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.

公开(公告)号：US12069856B2

公开(公告)日：2024-08-20

申请号：US18047214

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H10B41/27 ,  H10B41/10 ,  H10B51/00

CPC classification number: H10B41/27 ,  H10B51/00 ,  H10B41/10

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US11800717B2

公开(公告)日：2023-10-24

申请号：US17661659

申请日：2022-05-02

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L21/76 ,  H01L29/06 ,  H10B43/27 ,  H01L21/762

CPC classification number: H10B43/27 ,  H01L21/76224 ,  H01L29/0649

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20230061820A1

公开(公告)日：2023-03-02

申请号：US18047214

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11585

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US20220068955A1

公开(公告)日：2022-03-03

申请号：US17007951

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/06

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.

公开(公告)号：US20210375898A1

公开(公告)日：2021-12-02

申请号：US16887178

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11585

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US20190189576A1

公开(公告)日：2019-06-20

申请号：US16276533

申请日：2019-02-14

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/03011 ,  H01L2224/0345 ,  H01L2224/03921 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05186 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13021 ,  H01L2224/13026 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/01074

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US20190088637A1

公开(公告)日：2019-03-21

申请号：US15711937

申请日：2017-09-21

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L25/50 ,  H01L21/02021 ,  H01L21/02076 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/71 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.