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    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES
    12.
    发明申请
    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES 审中-公开

    公开(公告)号：US20200321317A1

    公开(公告)日：2020-10-08

    申请号：US16905435

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    Dual sided fan-out package having low warpage across all temperatures
    13.
    发明授权
    Dual sided fan-out package having low warpage across all temperatures 有权

    公开(公告)号：US10714456B2

    公开(公告)日：2020-07-14

    申请号：US16379078

    申请日：2019-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    Thrumold post package with reverse build up hybrid additive structure
    15.
    发明授权
    Thrumold post package with reverse build up hybrid additive structure 有权

    公开(公告)号：US10593568B2

    公开(公告)日：2020-03-17

    申请号：US16123158

    申请日：2018-09-06

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  John F. Kaeding ,  Ashok Pachamuthu ,  Mark E. Tuttle

    IPC: H01L21/56 ,  H01L23/31

    Abstract: Semiconductor devices having a semiconductor die electrically coupled to a redistribution structure and a molded material over the redistribution structure are disclosed herein, along with associated systems and methods. In one embodiment, a semiconductor device includes a semiconductor die attached to a first side of a substrate-free redistribution structure, and a plurality of conductive columns extending through a molded material disposed on the first side of the redistribution structure. The semiconductor device can also include a second redistribution structure on the molded material and electrically coupled to the conductive columns. A semiconductor device can be manufactured using a single carrier and requiring processing on only a single side of the semiconductor device.

    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES
    16.
    发明申请
    DUAL SIDED FAN-OUT PACKAGE HAVING LOW WARPAGE ACROSS ALL TEMPERATURES 审中-公开

    公开(公告)号：US20190237438A1

    公开(公告)日：2019-08-01

    申请号：US16379078

    申请日：2019-04-09

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00

    Abstract: Semiconductor devices including a dual-sided redistribution structure and having low-warpage across all temperatures and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die electrically coupled to a first side of a redistribution structure and a second semiconductor die electrically coupled to a second side of the redistribution structure opposite the first side. The semiconductor device also includes a first molded material on the first side, a second molded material on the second side, and conductive columns electrically coupled to the first side and extending through the first molded material. The first and second molded materials can have the same volume and/or coefficients of thermal expansion to inhibit warpage of the semiconductor device.

    Solder removal from semiconductor devices
    17.
    发明授权
    Solder removal from semiconductor devices 有权

    公开(公告)号：US10307850B2

    公开(公告)日：2019-06-04

    申请号：US15686008

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Mark E. Tuttle

    IPC: B23K31/02 ,  B23K1/018 ,  H01L23/00 ,  H01L21/66 ,  B23K101/40

    Abstract: A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.

    SOLDER REMOVAL FROM SEMICONDUCTOR DEVICES
    18.
    发明申请
    SOLDER REMOVAL FROM SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190061034A1

    公开(公告)日：2019-02-28

    申请号：US15686008

    申请日：2017-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Mark E. Tuttle

    IPC: B23K1/018 ,  H01L23/00 ,  H01L21/66

    Abstract: A solder removal apparatus is provided. The solder removal apparatus comprises a plurality of solder-interfacing protrusions extending from a body by a length. Each of the plurality of solder-interfacing protrusions is configured to remove a corresponding one of a plurality of solder features from a semiconductor device, where each of the plurality of solder features has a height and an amount of solder material.

    Stress tuned stiffeners for micro electronics package warpage control
    19.
    发明授权
    Stress tuned stiffeners for micro electronics package warpage control 有权

    公开(公告)号：US11581231B2

    公开(公告)日：2023-02-14

    申请号：US16447835

    申请日：2019-06-20

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Mark E. Tuttle

    IPC: H01L23/31 ,  H01L23/00 ,  H01L21/66 ,  H01L23/18 ,  H01L23/373 ,  H01L23/16

    Abstract: A semiconductor device assembly including a substrate, a semiconductor device, a stiffener member, and mold compound. The stiffener member is tuned, or configured, to reduce and/or control the shape of warpage of the semiconductor device assembly at an elevated temperature. The stiffener member may be placed on the substrate, on the semiconductor device, and/or on the mold compound. A plurality of stiffener members may be used. The stiffener members may be positioned in a predetermined pattern on a component of the semiconductor device assembly. A stiffener member may be used so that the warpage of a first semiconductor device substantially corresponds to the warpage of a second semiconductor device at an elevated temperature. The stiffener member may be tuned by providing the member with a desired coefficient of thermal expansion (CTE). The desired CTE may be based on the individual CTEs of the components of a semiconductor device assembly.

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