公开(公告)号：US20250140303A1

公开(公告)日：2025-05-01

申请号：US18751894

申请日：2024-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Takashi Tomatsu ,  Masaru Morohashi ,  Hideo Shimizu

IPC: G11C11/4076 ,  G11C11/4096

Abstract: An example apparatus includes a first circuit configured to activate a first control signal, a second circuit configured to activate a first timing signal after receiving the first control signal, a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit, a first signal line conveying the first control signal from the first circuit to the second circuit, a second signal line conveying the first timing signal from the second circuit to the third circuit, and a third signal line conveying the first timing signal from the third circuit to the second circuit. Each of the first to third signal lines is provided on first and second tracks extending in parallel with each other.

公开(公告)号：US11694738B2

公开(公告)日：2023-07-04

申请号：US17443056

申请日：2021-07-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi ,  Ryo Nagoshi ,  Yuan He ,  Yutaka Ito

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40611

Abstract: Apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

公开(公告)号：US11043254B2

公开(公告)日：2021-06-22

申请号：US16358587

申请日：2019-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/408 ,  G11C11/406 ,  G06F7/58

Abstract: An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US20190385667A1

公开(公告)日：2019-12-19

申请号：US16012679

申请日：2018-06-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi ,  Ryo Nagoshi ,  Yuan He ,  Yutaka Ito

IPC: G11C11/406

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for generating multiple row hammer address refresh sequences. An example apparatus may include an address scrambler and a refresh control circuit. The address scrambler may receive a first address, output a second address in response to a first control signal, and output a third address in response to a second control signal. The second address may physically adjacent to the first address and the third address may physically adjacent to the second address. The refresh control circuit may perform a refresh operation on the second address when the first control signal is active and perform the refresh operation on the third address when the second control signal is active.

公开(公告)号：US20180254074A1

公开(公告)日：2018-09-06

申请号：US15973061

申请日：2018-05-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi

IPC: G11C7/10 ,  G11C8/12 ,  G11C7/24 ,  G11C7/20

CPC classification number: G11C7/1087 ,  G11C7/1084 ,  G11C7/20 ,  G11C7/24 ,  G11C8/12

Abstract: Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes a identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.

公开(公告)号：US20160372170A1

公开(公告)日：2016-12-22

申请号：US14746435

申请日：2015-06-22

Applicant: Micron Technology, Inc.

Inventor： Masaru Morohashi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1084 ,  G11C7/20 ,  G11C7/24 ,  G11C8/12

Abstract: Apparatuses, methods, memory packages, and semiconductor chips are disclosed. An example apparatus includes a semiconductor chip including a layer identification setting path circuit configured to receive respective input signals from a plurality of input layer identification setting paths. The layer identification setting path circuit is further configured to change a value of at least one of the respective input signals to generate respective output signals and to provide the respective output signals to a plurality of output layer identification setting paths. The apparatus further includes a identification circuit configured to determine identification information based on the respective input signals and to compare the identification information to received access layer identification information. The identification circuit is configured to process received command signals based on the comparison between the identification information and the access layer identification information.

Abstract translation: 公开了装置，方法，存储器封装和半导体芯片。 示例性装置包括：半导体芯片，其包括层识别设置路径电路，被配置为从多个输入层识别设置路径接收相应的输入信号。 层识别设置路径电路还被配置为改变相应输入信号中的至少一个的值以产生相应的输出信号，并将各个输出信号提供给多个输出层识别设置路径。 所述装置还包括：识别电路，被配置为基于各个输入信号确定识别信息，并将所述识别信息与接收到的接入层识别信息进行比较。 识别电路被配置为基于识别信息和接入层识别信息之间的比较来处理接收到的命令信号。

公开(公告)号：US11222682B1

公开(公告)日：2022-01-11

申请号：US17007069

申请日：2020-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406

Abstract: Apparatuses and methods for generating refresh addresses for row hammer refresh operations are disclosed. In some examples, determination of a row address associated with a highest count value may be initiated at a precharge command preceding a row hammer refresh operation. The row address determined to be associated with the highest count value may be provided for generating the refresh addresses.

公开(公告)号：US20210225432A1

公开(公告)日：2021-07-22

申请号：US17301533

申请日：2021-04-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Honoka Enomoto ,  Masaru Morohashi

IPC: G11C11/406 ,  G06F7/58 ,  G11C11/408

Abstract: Disclosed herein is an apparatus that includes a plurality of address registers each storing an address signal, a plurality of counter circuits each storing a count value corresponding to an associated one of the address registers, a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

公开(公告)号：US10910034B2

公开(公告)日：2021-02-02

申请号：US16538603

申请日：2019-08-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Masaru Morohashi

IPC: G11C11/406 ,  G11C11/408 ,  G11C29/00 ,  G11C11/4097 ,  G11C11/4074 ,  G11C11/4076

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes producing, responsive to a first refresh command, a plurality of first refresh addresses and detecting, responsive to the plurality of first refresh addresses, that the plurality of first refresh addresses include a first defective address and a first non-defective address. The example method further includes refreshing, responsive to a second refresh command following the first refresh command, the non-defective first address without refreshing the first defective address.

公开(公告)号：US20190228815A1

公开(公告)日：2019-07-25

申请号：US15876566

申请日：2018-01-22

Applicant: Micron Technology, Inc.

Inventor： Masaru Morohashi ,  Hidekazu Noguchi

IPC: G11C11/406 ,  G11C15/04 ,  G11C8/10 ,  G11C16/34 ,  G06F13/16

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.